| 2001 | Software-Assisted Cache Replacement Mechanisms for Embedded Systems. | Prabhat Jain, Srinivas Devadas, Daniel W. Engels, Larry Rudolph |
| 2001 | CASh: A Novel "Clock as Shield" Design Methodology for Noise Immune Precharge-Evaluate Logic. | Yonghee Im, Kaushik Roy |
| 2001 | A Methodology for the Design of Application Specific Instruction Set Processors (ASIP) using the Machine Description Language LISA. | Andreas Hoffmann, Oliver Schliebusch, Achim Nohl, Gunnar Braun, Oliver Wahlen, Heinrich Meyr |
| 2001 | BOOM - A Heuristic Boolean Minimizer. | Jan Hlavicka, Petr Fiser |
| 2001 | Model Reduction of Variable-Geometry Interconnects using Variational Spectrally-Weighted Balanced Truncation. | Payam Heydari, Massoud Pedram |
| 2001 | A System for Synthesizing Optimized FPGA Hardware from MATLAB. | Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee |
| 2001 | Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. | Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zhang, Sharad Malik |
| 2001 | The Sizing Rules Method for Analog Integrated Circuit Design. | Helmut E. Graeb, Stephan Zizala, Josef Eckmller, Kurt Antreich |
| 2001 | Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. | Wilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli |
| 2001 | Direct Transistor-Level Layout for Digital Blocks. | Prakash Gopalakrishnan, Rob A. Rutenbar |
| 2001 | False-Noise Analysis using Logic Implications. | Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Supamas Sirichotiyakul, Chanhee Oh, Vladimir Zolotov |
| 2001 | System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip. | Tony Givargis, Frank Vahid, Jrg Henkel |
| 2001 | Local Search for Final Placement in VLSI Design. | Oluf Faroe, David Pisinger, Martin Zachariasen |
| 2001 | A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. | Nak-Woong Eum, Taewhan Kim, Chong-Min Kyung |
| 2001 | Techniques for Including Dielectrics when Extracting Passive Low-Order Models of High Speed Interconnect. | Luca Daniel, Alberto L. Sangiovanni-Vincentelli, Jacob K. White |
| 2001 | Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing. | Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen |
| 2001 | Multilevel Approach to Full-Chip Gridless Routing. | Jason Cong, Jie Fang, Yan Zhang VI |
| 2001 | A Convex Programming Approach to Positive Real Rational Approximation. | Carlos P. Coelho, Joel R. Phillips, Lus Miguel Silveira |
| 2001 | Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. | Jovanka Ciric, Carl Sechen |
| 2001 | Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects. | TingYen Chiang, Kaustav Banerjee, Krishna Saraswat |
| 2001 | Non-linear Quantification Scheduling in Image Computation. | Pankaj Chauhan, Edmund M. Clarke, Somesh Jha, James H. Kukula, Thomas R. Shiple, Helmut Veith, Dong Wang |
| 2001 | Practical Considerations in RLCK Crosstalk Analysis for Digital Integrated Circuits. | Steven C. Chan, Kenneth L. Shepard |
| 2001 | Single-Pass Redundancy Addition and Removal. | Chih-Wei Jim Chang, Malgorzata Marek-Sadowska |
| 2001 | Induction-Based Gate-Level Verification of Multipliers. | Ying-Tsai Chang, Kwang-Ting Cheng |
| 2001 | Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. | Subash Chandar G., Mahesh Mehendale, R. Govindarajan |