| 2000 | Design-Manufacturing Interface for 0.13 Micron and Below. | Andrzej J. Strojwas |
| 2000 | Timing Driven Gate Duplication: Complexity Issues and Algorithms. | Ankur Srivastava, Ryan Kastner, Majid Sarrafzadeh |
| 2000 | Bus Energy Minimization by Transition Pattern Coding (TPC) in Deep Submicron Technologies. | Paul-Peter Sotiriadis, Anantha P. Chandrakasan |
| 2000 | Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. | Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai |
| 2000 | Full-Chip, Three-Dimensional, Shapes-Based RLC Extraction. | Kenneth L. Shepard, Dipak Sitaram, Yu Zheng |
| 2000 | Power Exploration for Embedded VLIW Architectures. | Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria |
| 2000 | Verification of Delta-Sigma Converters Using Adaptive Regression Modeling. | Jeongjin Roh, Suresh Seshadri, Jacob A. Abraham |
| 2000 | Latency Effects of System Level Power Management Algorithms. | Dinesh Ramanathan, Sandy Irani, Rajesh K. Gupta |
| 2000 | Challenges and Opportunities in Broadband and Wireless Communication Designs. | Jan M. Rabaey, Miodrag Potkonjak, Farinaz Koushanfar, Suet-Fei Li, Tim Tuan |
| 2000 | A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits. | Michael Pronath, Volker Gloeckel, Helmut E. Graeb |
| 2000 | Simulation Based Test Generation for Scan Designs. | Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Challenges in Physical Chip Design. | Ralph H. J. M. Otten, Paul Stravers |
| 2000 | Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. | Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu |
| 2000 | An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. | Arlindo L. Oliveira, Rajeev Murgai |
| 2000 | System and Architecture-Level Power Reduction for Microprocessor-Based Communication and Multi-Media Applications. | Lode Nachtergaele, Vivek Tiwari, Nikil D. Dutt |
| 2000 | Layout-Driven Area-Constrained Timing Optimization by Net Buffering. | Rajeev Murgai |
| 2000 | A Force-Directed Macro-Cell Placer. | Fan Mo, Abdallah Tabbara, Robert K. Brayton |
| 2000 | Noise Analysis of Phase-Locked Loops. | Amit Mehrotra |
| 2000 | Event Driven Simulation Without Loops or Conditionals. | Peter M. Maurer |
| 2000 | Power-Conscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Real-Time Embedded Systems. | Jiong Luo, Niraj K. Jha |
| 2000 | Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. | Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng |
| 2000 | ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters. | Erik Lauwers, Georges G. E. Gielen |
| 2000 | Efficient Exploration of the SoC Communication Architecture Design Space. | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
| 2000 | Regularity Driven Logic Synthesis. | Thomas Kutzschebauch, Leon Stok |
| 2000 | Delay Budgeting for a Timing-Closure-Driven Design Method. | Chien-Chu Kuo, Allen C.-H. Wu |