| 2000 | Transistor-Level Timing Analysis Using Embedded Simulation. | Pawan Kulshreshtha, Robert Palermo, Mohammad Mortazavi, Cyrus Bamji, Hakan Yalcin |
| 2000 | Generalized Symmetries in Boolean Functions. | Victor N. Kravets, Karem A. Sakallah |
| 2000 | Symbolic Debugging Scheme for Optimized Hardware and Software. | Farinaz Koushanfar, Darko Kirovski, Miodrag Potkonjak |
| 2000 | A Methodology for Verifying Memory Access Protocols in Behavioral Synthesis. | Gernot Koch, Taewhan Kim, Reiner Genevriere |
| 2000 | Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering. | Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas |
| 2000 | Fast Test Application Technique Without Fast Scan Clocks. | Seonki Kim, Bapiraju Vinnakota |
| 2000 | Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. | Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang |
| 2000 | Pipeline Optimization for Asynchronous Circuits: Complexity Analysis and an Efficient Optimal Algorithm. | Sangyun Kim, Peter A. Beerel |
| 2000 | Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. | Sunil P. Khatri, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 2000 | Predictable Routing. | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh |
| 2000 | An "Effective" Capacitance Based Delay Metric for RC Interconnect. | Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan |
| 2000 | FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders. | Hyeong-Ju Kang, Hansoo Kim, In-Cheol Park |
| 2000 | On Mismatches between Incremental Optimizers and Instance Perturbations in Physical Design Tools. | Andrew B. Kahng, Stefanus Mantik |
| 2000 | Don't Cares and Multi-Valued Logic Network Minimization. | Yunjian Jiang, Robert K. Brayton |
| 2000 | Exploring Performance Tradeoffs for Clustered VLIW ASIPs. | Margarida F. Jacome, Gustavo de Veciana, Viktor S. Lapinskii |
| 2000 | Achieving Fast and Exact Hazard-Free Logic Minimization of Extended Burst-Mode gC Finite State Machines. | Hans M. Jacobson, Chris J. Myers, Ganesh Gopalakrishnan |
| 2000 | Simulation Coverage Enhancement Using Test Stimulus Transformations. | C. Norris Ip |
| 2000 | Test Generation for Acyclic Sequential Circuits with Hold Registers. | Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara |
| 2000 | A Timing-Constrained Algorithm for Simultaneous Global Routing of Multiple Nets. | Jiang Hu, Sachin S. Sapatnekar |
| 2000 | MONGREL: Hybrid Techniques for Standard Cell Placement. | Sung-Woo Hur, John Lillis |
| 2000 | Improving the Proportion of At-Speed Tests in Scan BIST. | Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski |
| 2000 | Smart Simulation Using Collaborative Formal and Simulation Engines. | Pei-Hsin Ho, Thomas R. Shiple, Kevin Harer, James H. Kukula, Robert F. Damiano, Valeria Bertacco, Jerry Taylor, Jiang Long |
| 2000 | Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method. | Sungpack Hong, Taewhan Kim |
| 2000 | Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
| 2000 | Synthesis of Operation-Centric Hardware Descriptions. | James C. Hoe, Arvind |