| 2020 | Faultless to a Fault? The Case of Threshold Implementations of Crypto-systems vs Fault Template Attacks. | Debdeep Mukhopadhyay |
| 2020 | HyperFuzzing for SoC Security Validation. | Sujit Kumar Muduli, Gourav Takhar, Pramod Subramanyan |
| 2020 | Early-stage Automated Accelerator Identification Tool for Embedded Systems with Limited Area. | Parnian Mokri, Mark Hempstead |
| 2020 | SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning Accelerators. | Marco Minutoli, Vito Giovanni Castellana, Cheng Tan, Joseph B. Manzano, Vinay Amatya, Antonino Tumeo, David Brooks, Gu-Yeon Wei |
| 2020 | NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule Networks. | Alberto Marchisio, Andrea Massa, Vojtech Mrazek, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique |
| 2020 | Agile SoC Development with Open ESP : Invited Paper. | Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni |
| 2020 | Performance Analysis of Priority-Aware NoCs with Deflection Routing under Traffic Congestion. | Sumit K. Mandal, Anish Krishnakumar, Raid Ayoub, Michael Kishinevsky, mit Y. Ogras |
| 2020 | A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGA. | Yukui Luo, Xiaolin Xu |
| 2020 | A Fast Learning-Driven Signoff Power Optimization Framework. | Yi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim |
| 2020 | HitM: High-Throughput ReRAM-based PIM for Multi-Modal Neural Networks. | Bing Li, Ying Wang, Yiran Chen |
| 2020 | Concurrent Weight Encoding-based Detection for Bit-Flip Attack on Neural Network Accelerators. | Qi Liu, Wujie Wen, Yanzhi Wang |
| 2020 | Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. | Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen |
| 2020 | Hardware Acceleration of Robot Scene Perception Algorithms. | Yanqi Liu, Can Eren Derman, Giuseppe Calderoni, R. Iris Bahar |
| 2020 | MLCache: A Space-Efficient Cache Scheme based on Reuse Distance and Machine Learning for NVMe SSDs. | Weiguang Liu, Jinhua Cui, Junwei Liu, Laurence T. Yang |
| 2020 | Overview of 2020 CAD Contest at ICCAD. | Ing-Chao Lin, Ulf Schlichtmann, Tsung-Wei Huang, Mark Po-Hung Lin |
| 2020 | Retiming for High-performance Superconductive Circuits with Register Energy Minimization. | Ting-Ru Lin, Massoud Pedram |
| 2020 | Symbolic Uniform Sampling with XOR Circuits. | Yen-Ting Lin, Jie-Hong R. Jiang, Victor N. Kravets |
| 2020 | Mining Biochemical Circuits from Enzyme Databases via Boolean Reasoning. | Yu-Chou Lin, Jie-Hong R. Jiang |
| 2020 | Achieving Analog Layout Integrity through Learning and Migration Invited Talk. | Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen |
| 2020 | GPU Acceleration in VLSI Back-end Design: Overview and Case Studies. | Yibo Lin |
| 2020 | MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. | Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera |
| 2020 | A Customized Graph Neural Network Model for Guiding Analog IC Placement. | Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu |
| 2020 | Routing-Free Crosstalk Prediction. | Rongjian Liang, Zhiyao Xie, Jinwook Jung, Vishnavi Chauha, Yiran Chen, Jiang Hu, Hua Xiang, Gi-Joon Nam |
| 2020 | Leveraging Weakly-hard Constraints for Improving System Fault Tolerance with Functional and Timing Guarantees. | Hengyi Liang, Zhilu Wang, Ruochen Jiao, Qi Zhu |
| 2020 | DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators. | Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li |