| 2011 | A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis. | Yu Wang, Mo Xu, Ling Ren, Xiaorui Zhang, Di Wu, Yong He, Ningyi Xu, Huazhong Yang |
| 2011 | Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management. | Hai Wang, Sheldon X.-D. Tan, Guangdeng Liao, Rafael Quintanilla, Ashish Gupta |
| 2011 | A theoretical probabilistic simulation framework for dynamic power estimation. | Lei Wang, Markus Olbrich, Erich Barke, Thomas Bchner, Markus Bhler, Philipp V. Panitz |
| 2011 | The approximation scheme for peak power driven voltage partitioning. | Jia Wang, Xiaodao Chen, Chen Liao, Shiyan Hu |
| 2011 | MACACO: Modeling and analysis of circuits for approximate computing. | Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan |
| 2011 | Automatic formal verification of multithreaded pipelined microprocessors. | Miroslav N. Velev, Ping Gao |
| 2011 | Failure diagnosis of asymmetric aging under NBTI. | Jyothi Bhaskarr Velamala, Venkatesa Ravi, Yu Cao |
| 2011 | A corner stitching compliant B | Hui-Fang Tsao, Pang-Yen Chou, Shih-Lun Huang, Yao-Wen Chang, Mark Po-Hung Lin, Duan-Ping Chen, Dick Liu |
| 2011 | GPU programming for EDA with OpenCL. | Rasit Onur Topaloglu, Benedict R. Gaster |
| 2011 | Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs. | Vasileios Tenentes, Xrysovalantis Kavousianos |
| 2011 | Optimal layout decomposition for double patterning technology. | Xiaoping Tang, Minsik Cho |
| 2011 | The future of clock network synthesis. | Cliff C. N. Sze |
| 2011 | Defect-tolerant logic implementation onto nanocrossbars by exploiting mapping and morphing simultaneously. | Yehua Su, Wenjing Rao |
| 2011 | The STeTSiMS STT-RAM simulation and modeling system. | Clinton Wills Smullen IV, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan |
| 2011 | PTrace: Derivative-free local tracing of bicriterial design tradeoffs. | Amith Singhee |
| 2011 | Keynote address: Design of secure systems - Where are the EDA tools? | Georg Sigl |
| 2011 | Congestion analysis for global routing via integer programming. | Hamid Shojaei, Azadeh Davoodi, Jeffrey T. Linderoth |
| 2011 | Inferring assertion for complementary synthesis. | ShengYu Shen, Ying Qin, Jianmin Zhang |
| 2011 | Application-aware deadlock-free oblivious routing based on extended turn-model. | Ali Shafiee, Mahdy Zolghadr, Mohammad Arjomand, Hamid Sarbazi-Azad |
| 2011 | Alternative design methodologies for the next generation logic switch. | Davide Sacchetto, Michele De Marchi, Giovanni De Micheli, Yusuf Leblebici |
| 2011 | Temperature aware statistical static timing analysis. | Artem Rogachev, Lu Wan, Deming Chen |
| 2011 | Accelerating RTL simulation with GPUs. | Hao Qian, Yangdong Deng |
| 2011 | Hybrid CMOS/Magnetic Process Design Kit and application to the design of high-performances non-volatile logic circuits. | Guillaume Prenat, Bernard Dieny, Jean-Pierre Nozieres, Gregory di Pendina, Kholdoun Torki |
| 2011 | Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs. | Mohit Pathak, Jiwoo Pak, David Z. Pan, Sung Kyu Lim |
| 2011 | Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. | Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin |