| 2011 | Gate sizing and device technology selection algorithms for high-performance industrial designs. | Muhammet Mustafa Ozdal, Steven M. Burns, Jiang Hu |
| 2011 | Massively parallel programming models used as hardware description languages: The OpenCL case. | Muhsen Owaida, Nikolaos Bellas, Christos D. Antonopoulos, Konstantis Daloukas, Charalambos Antoniadis |
| 2011 | Delay optimization using SOP balancing. | Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets |
| 2011 | Structure preserving reduced-order modeling of linear periodic time-varying systems. | Ting Mei, Heidi Thornquist, Eric R. Keiter, Scott A. Hutchinson |
| 2011 | Progress in CMOS-memristor integration. | Gilberto Medeiros-Ribeiro, Janice H. Nickel, J. Joshua Yang |
| 2011 | Algorithmic tuning of clock trees and derived non-tree structures. | Igor L. Markov, Dong-Jin Lee |
| 2011 | Debugging with dominance: On-the-fly RTL debug solution implications. | Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour |
| 2011 | High-quality global routing for multiple dynamic supply voltage designs. | Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao |
| 2011 | Towards completely automatic decoder synthesis. | Hsiou-Yuan Liu, Yen-Cheng Chou, Chen-Hsuan Lin, Jie-Hong R. Jiang |
| 2011 | Detecting stability faults in sub-threshold SRAMs. | Chen-Wei Lin, Hao-Yu Yang, Chin-Yuan Huang, Hung-Hsin Chen, Mango Chia-Tso Chao |
| 2011 | Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. | Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li |
| 2011 | Variation-aware electromigration analysis of power/ground networks. | Di-An Li, Malgorzata Marek-Sadowska |
| 2011 | CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. | Sheng Li, Ke Chen, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi |
| 2011 | Fast statistical timing analysis for circuits with Post-Silicon Tunable clock buffers. | Bing Li, Ning Chen |
| 2011 | 2011 TAU power grid simulation contest: Benchmark suite and results. | Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif |
| 2011 | Multilevel tree fusion for robust clock networks. | Dong-Jin Lee, Igor L. Markov |
| 2011 | High-level synthesis with distributed controller for fast timing closure. | Seokhyun Lee, Kiyoung Choi |
| 2011 | REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations. | Charles Lamech, Jim Aarestad, Jim Plusquellic, Reza M. Rad, Kanak Agarwal |
| 2011 | In-system and on-the-fly clock tuning mechanism to combat lifetime performance degradation. | Zahra Lak, Nicola Nicolici |
| 2011 | On proving the efficiency of alternative RF tests. | Nathan Kupp, Haralampos-G. D. Stratigopoulos, Petros Drineas, Yiorgos Makris |
| 2011 | On rewiring and simplification for canonicity in threshold logic circuits. | Pin-Yi Kuo, Chun-Yao Wang, Ching-Yi Huang |
| 2011 | Neuromorphic modeling abstractions and simulation of large-scale cortical networks. | Jeffrey L. Krichmar, Nikil D. Dutt, Jayram Moorkanikara Nageswaran, Micah Richert |
| 2011 | Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. | Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian |
| 2011 | Co-design of channel buffers and crossbar organizations in NoCs architectures. | Avinash Karanth Kodi, Randy Morris, Dominic DiTomaso, Ashwini Sarathy, Ahmed Louri |
| 2011 | Balanced reconfiguration of storage banks in a hybrid electrical energy storage system. | Younghyun Kim, Sangyoung Park, Yanzhi Wang, Qing Xie, Naehyuck Chang, Massimo Poncino, Massoud Pedram |