| 2011 | A SimPLR method for routability-driven placement. | Myung-Chul Kim, Jin Hu, Dong-Jin Lee, Igor L. Markov |
| 2011 | Low-power multiple-bit upset tolerant memory optimization. | Seokjoong Kim, Matthew R. Guthaus |
| 2011 | Synchronous elasticization at a reduced cost: Utilizing the ultra simple fork and controller merging. | Eliyah Kilada, Kenneth S. Stevens |
| 2011 | A robust architecture for post-silicon skew tuning. | Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang |
| 2011 | Accelerated statistical simulation via on-demand Hermite spline interpolations. | Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif |
| 2011 | Improving shared cache behavior of multithreaded object-oriented applications in multicores. | Mahmut T. Kandemir, Shekhar Srikantaiah, Seung Woo Son |
| 2011 | Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC. | Moongon Jung, Xi Liu, Suresh K. Sitaraman, David Z. Pan, Sung Kyu Lim |
| 2011 | Universal statistical cure for predicting memory loss. | Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Li |
| 2011 | Efficient analytical macromodeling of large analog circuits by Transfer Function Trajectories. | Dimitri de Jonghe, Georges G. E. Gielen |
| 2011 | Mitigating FPGA interconnect soft errors by in-place LUT inversion. | Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He |
| 2011 | System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. | Haris Javaid, Muhammad Shafique, Jrg Henkel, Sri Parameswaran |
| 2011 | Chemical-mechanical polishing aware application-specific 3D NoC design. | Wooyoung Jang, Ou He, Jae-Seok Yang, David Z. Pan |
| 2011 | Fast statistical model of TiO2 thin-film memristor and design implication. | Miao Hu, Hai Li, Robinson E. Pino |
| 2011 | Match and replace - A functional ECO engine for multi-error circuit rectification. | Shao-Lun Huang, Wei-Hsun Lin, Chung-Yang (Ric) Huang |
| 2011 | Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips. | Tsung-Wei Huang, Tsung-Yi Ho, Krishnendu Chakrabarty |
| 2011 | Progress and outlook for STT-MRAM. | Yiming Huai, Yuchen Zhou, Ioan Tudosa, Roger Malmhall, Rajiv Ranjan, Jing Zhang |
| 2011 | Routability-driven analytical placement for mixed-size circuit designs. | Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, Yao-Wen Chang |
| 2011 | Escape routing for staggered-pin-array PCBs. | Yuan-Kai Ho, Hsu-Chieh Lee, Yao-Wen Chang |
| 2011 | Ripple: An effective routability-driven placer by iterative cell movement. | Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui, Evangeline F. Y. Young |
| 2011 | CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. | Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran |
| 2011 | Statistical aging analysis with process variation consideration. | Sangwoo Han, Joohee Choung, Byung-Su Kim, Bong Hyun Lee, Hungbok Choi, Juho Kim |
| 2011 | Exploring high throughput computing paradigm for global routing. | Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy |
| 2011 | Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization. | Junjun Gu, Gang Qu, Lin Yuan, Cheng Zhuo |
| 2011 | Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. | Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa |
| 2011 | A framework for double patterning-enabled design. | Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta |