| 2011 | A jumper insertion algorithm under antenna ratio and timing constraints. | Xin Gao, Luca Macchiarulo |
| 2011 | Modeling and estimation of power supply noise using linear programming. | Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori |
| 2011 | Clocking design automation in Intel's Core i7 and future designs. | Ali M. El-Husseini, Matthew Morrise |
| 2011 | Synthesis of parallel binary machines. | Elena Dubrova |
| 2011 | Optimizing data locality using array tiling. | Wei Ding, Yuanrui Zhang, Jun Liu, Mahmut T. Kandemir |
| 2011 | Post-silicon bug diagnosis with inconsistent executions. | Andrew DeOrio, Daya Shanker Khudia, Valeria Bertacco |
| 2011 | A framework for accelerating neuromorphic-vision algorithms on FPGAs. | Michael DeBole, Ahmed Al-Maashri, Matthew Cotter, Chi-Li Yu, Chaitali Chakrabarti, Vijaykrishnan Narayanan |
| 2011 | Combined loop transformation and hierarchy allocation for data reuse optimization. | Jason Cong, Peng Zhang, Yi Zou |
| 2011 | ATree-based topology synthesis for on-chip network. | Jason Cong, Yuhui Huang, Bo Yuan |
| 2011 | Assuring application-level correctness against soft errors. | Jason Cong, Karthik Gururaj |
| 2011 | A methodology for local resonant clock synthesis using LC-assisted local clock buffers. | Walter James Condley, Xuchu Hu, Matthew R. Guthaus |
| 2011 | Identifying the optimal energy-efficient operating points of parallel workloads. | Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda |
| 2011 | PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. | Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu |
| 2011 | Useful-skew clock optimization for multi-power mode designs. | Hsuan-Ming Chou, Hao Yu, Shih-Chieh Chang |
| 2011 | On the preconditioner of conjugate gradient method - A power grid simulation perspective. | Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang |
| 2011 | Heterogeneous B | Pang-Yen Chou, Hung-Chih Ou, Yao-Wen Chang |
| 2011 | A low-swing crossbar and link generator for low-power networks-on-chip. | Chia-Hsin Owen Chen, Sunghyun Park, Tushar Krishna, Li-Shiuan Peh |
| 2011 | Simulation-based signal selection for state restoration in silicon debug. | Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco |
| 2011 | Timing ECO optimization via Bzier curve smoothing and fixability identification. | Hua-Yu Chang, Iris Hui-Ru Jiang, Yao-Wen Chang |
| 2011 | The role of EDA in digital print automation and infrastructure optimization. | Krishnendu Chakrabarty, Gary Dispoto, Rick Bellamy, Jun Zeng |
| 2011 | A trace compression algorithm targeting power estimation of long benchmarks. | Andrey Ayupov, Steven M. Burns |
| 2011 | ModSpec: An open, flexible specification framework for multi-domain device modelling. | David Amsallem, Jaijeet S. Roychowdhury |
| 2011 | Formal verification of phase-locked loops using reachability analysis and continuization. | Matthias Althoff, Soner Yaldiz, Akshay Rajhans, Xin Li, Bruce H. Krogh, Larry T. Pileggi |
| 2010 | Active learning framework for post-silicon variation extraction and test cost reduction. | Cheng Zhuo, Kanak Agarwal, David T. Blaauw, Dennis Sylvester |
| 2010 | Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation. | Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar |