| 2010 | Engineering a scalable Boolean matching based on EDA SaaS 2.0. | Chun Zhang, Yu Hu, Lingli Wang, Lei He, Jiarong Tong |
| 2010 | Electrical characterization of RF TSV for 3D multi-core and heterogeneous ICs. | Le Yu, Haigang Yang, Tom T. Jing, Min Xu, Robert E. Geer, Wei Wang |
| 2010 | On timing-independent false path identification. | Feng Yuan, Qiang Xu |
| 2010 | WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography. | Kun Yuan, David Z. Pan |
| 2010 | Simulation of random telegraph Noise with 2-stage equivalent circuit. | Yun Ye, Chi-Chao Wang, Yu Cao |
| 2010 | On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation. | Xiaoji Ye, Peng Li |
| 2010 | On the escape routing of differential pairs. | Tan Yan, Pei-Ci Wu, Qiang Ma, Martin D. F. Wong |
| 2010 | Recent research development in PCB layout. | Tan Yan, Martin D. F. Wong |
| 2010 | Structured analog circuit design and MOS transistor decomposition for high accuracy applications. | Bo Yang, Qing Dong, Jing Li, Shigetoshi Nakatake |
| 2010 | Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs. | Hao Xu, Ranga Vemuri, Wen-Ben Jone |
| 2010 | Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping. | Hao Xu, Wen-Ben Jone, Ranga Vemuri |
| 2010 | An auction based pre-processing technique to determine detour in global routing. | Yue Xu, Chris Chu |
| 2010 | A hierarchical matrix inversion algorithm for vectorless power grid verification. | Xuanxing Xiong, Jia Wang |
| 2010 | Practical placement and routing techniques for analog circuit designs. | Linfu Xiao, Evangeline F. Y. Young, Xiao-Yong He, Kong-Pang Pun |
| 2010 | Local clock skew minimization using blockage-aware mixed tree-mesh clock network. | Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian, Evangeline F. Y. Young |
| 2010 | A robust functional ECO engine by SAT proof minimization and interpolation techniques. | Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang |
| 2010 | A scalable quantitative measure of IR-drop effects for scan pattern generation. | Meng-Fan Wu, Kun-Han Tsai, Wu-Tung Cheng, Hsin-Cheih Pan, Jiun-Lang Huang, Augusli Kifli |
| 2010 | Scalable segmentation-based malicious circuitry detection and diagnosis. | Sheng Wei, Miodrag Potkonjak |
| 2010 | HW/SW co-design of parallel systems. | Enno Wein |
| 2010 | PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation. | Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, Grantham K. H. Pang, Ngai Wong |
| 2010 | The fast optimal voltage partitioning algorithm for peak power density minimization. | Jia Wang, Shiyan Hu |
| 2010 | Analysis of circuit dynamic behavior with timed ternary decision diagram. | Lu Wan, Deming Chen |
| 2010 | 3POr - Parallel projection based parameterized order reduction for multi-dimensional linear models. | Jorge Fernandez Villena, Lus Miguel Silveira |
| 2010 | A lower bound computation method for evaluation of statistical design techniques. | Vineeth Veetil, Dennis Sylvester, David T. Blaauw |
| 2010 | Design of large area electronics with organic transistors. | Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai |