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IEEE International Conference on Computer Design

ICCD

C

CORE rank

CORE rank (raw)

C

Fields of research

Computer Systems Engineering

Papers indexed

3,768

1988–2025

Papers per year

1988128 peak2025

ICCD papers

3,768 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2003NpBench: A Benchmark Suite for Control plane and Data plane Applications for Network Processors.Byeong Kil Lee, Lizy Kurian John
2003CMOS High-Speed I/Os - Present and Future.Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton
2003Hardware-based Pointer Data Prefetcher.Shih-Chang Lai, Shih-Lien Lu
2003SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture.Young-Su Kwon, Bong-Il Park, Chong-Min Kyung
2003Distributed Reorder Buffer Schemes for Low Power.Gurhan Kucuk, Oguz Ergin, Dmitry Ponomarev, Kanad Ghose
2003Care Bit Density and Test Cube Clusters: Multi-Level Compression Opportunities.Bernd Knemann
2003Fully Differential Receiver Chipset for 40 Gb/s Applications Using GaInAs/InP Single Heterojunction Bipolar Transistors.Kursad Kiziloglu, Shivakumar Seetharaman, K. W. Glass, C. Bil, H. V. Duong, G. Asmanis
2003System LSI Implementation Fabrics for the Future (special panel discussion).Sinan Kaptanoglu
2003Design and Performance of Compressed Interconnects for High Performance Servers.Krishna Kant, Ravishankar K. Iyer
2003Interconnect Estimation for FPGAs under Timing Driven Domains.PariVallal Kannan, Dinesh Bhatia
2003Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.Dongku Kang, Mark C. Johnson, Kaushik Roy
2003On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume.Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty
2003Design Flow Enhancements for DNA Arrays.Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky
2003A Physical Design Methodology for 1.3GHz SPARC64 Microprocessor.Noriyuki Ito, Hiroaki Komatsu, Yoshiyasu Tanamura, Ryoichi Yamashita, Hiroyuki Sugiyama, Yaroku Sugiyama, Hirofumi Hamamura
2003Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition.Masayuki Ito, David G. Chinnery, Kurt Keutzer
2003An Improved method for Fast Noise Estimation based on Net Segmentation.Chih-Liang Huang, Aurobindo Dasgupta
2003High-Speed Link Design, Then and Now.Mark Horowitz
2003A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz
2003Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor.Joel Grodstein, Dilip K. Bhavsar, Vijay Bettada, Richard A. Davies
2003KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths.Chandramouli Gopalakrishnan, Srinivas Katkoori
2003Dynamic Cluster Resizing.Jos Gonzlez, Antonio Gonzlez
2003An Energy-Aware Simulation Model and Transaction Protocol for Dynamic Workload Distribution in Mobile Ad Hoc Networks.Farhad Ghasemi-Tari, Peng Rong, Massoud Pedram
2003A Study of Hardware Techniques That Dynamically Exploit Frequent Operands to Reduce Power Consumption in Integer Function Units.Kaushal R. Gandhi, Nihar R. Mahapatra
2003Pipelined Multiplicative Division with IEEE Rounding.Guy Even, Peter-Michael Seidel
2003A Mixed-Mode Delay-Locked-Loop Architecture.Daniel Eckerbert, Lars J. Svensson, Per Larsson-Edefors
2,1512,175 of 3,768← PreviousNext →

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