| 2003 | A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. | N. Ranganathan, Ashok K. Murugavel |
| 2003 | Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. | Janusz Rajski, Jerzy Tyszer |
| 2003 | An Efficient Algorithm for Calculating the Worst-case Delay due to Crosstalk. | Venkatesan Rajappan, Sachin S. Sapatnekar |
| 2003 | Charge-Recycling Voltage Domains for Energy-Efficient Low-Voltage Operation of Digital CMOS Circuits. | Saravanan Rajapandian, Zheng Xu, Kenneth L. Shepard |
| 2003 | Terascale Computing and BlueGene. | William R. Pulleyblank |
| 2003 | Static Test Compaction for Multiple Full-Scan Circuits. | Irith Pomeranz, Sudhakar M. Reddy |
| 2003 | Efficient Synthesis of Networks On Chip. | Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli |
| 2003 | Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. | Marong Phadoongsidhi, Kewal K. Saluja |
| 2003 | Virtual Page Tag Reduction for Low-power TLBs. | Peter Petrov, Alex Orailoglu |
| 2003 | Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches. | Sudeep Pasricha, Alexander V. Veidenbaum |
| 2003 | Cost-Efficient Memory Architecture Design of NAND Flash Memory Embedded Systems. | Chanik Park, Jaeyu Seo, Dongyoung Seo, Shinhan Kim, Bumsoo Kim |
| 2003 | Simplifying SoC design with the Customizable Control Processor Platform. | C. Ross Ogilvie, Richard Ray, Robert Devins, Mark Kautzman, Michael Hale, Reinaldo A. Bergamaschi, Bob Lynch, Santosh Gaur |
| 2003 | Power-Time Tradeoff in Test Scheduling for SoCs. | Mehrdad Nourani, James Chin |
| 2003 | A Dependence Driven Efficient Dispatch Scheme. | Sriram Nadathur, Akhilesh Tyagi |
| 2003 | A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. | Madhubanti Mukherjee, Ranga Vemuri |
| 2003 | Profiling Interrupt Handler Performance through Kernel Instrumentation. | Branden J. Moore, Thomas Slabach, Lambert Schaelicke |
| 2003 | Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi |
| 2003 | XMAX: X-Tolerant Architecture for MAXimal Test Compression. | Subhasish Mitra, Kee Sup Kim |
| 2003 | Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis. | Nihar R. Mahapatra, Jiangjiang Liu, Krishnan Sundaresan |
| 2003 | Interface Synthesis using Memory Mapping for an FPGA Platform. | Manev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau |
| 2003 | Reducing Multimedia Decode Power using Feedback Control. | Zhijian Lu, John C. Lach, Mircea R. Stan, Kevin Skadron |
| 2003 | Paradigm Shift For Jitter and Noise In Design and Test > GB/s Communication Systems. | Mike Peng Li, Jan B. Wilstrup |
| 2003 | Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach. | Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha |
| 2003 | An Efficient VLIW DSP Architecture for Baseband Processing. | Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen |
| 2003 | Detection of Biological Molecules: From Self-Assembled Films to Self-Integrated Devices. | Rastislav Levicky |