| 1998 | Optimizing the DRAM refresh count for merged DRAM/logic LSIs. | Taku Ohsawa, Koji Kai, Kazuaki J. Murakami |
| 1998 | A low power SRAM using auto-backgate-controlled MT-CMOS. | Koji Nii, Hiroshi Makino, Yoshiki Tsujihashi, Chikayoshi Morishima, Yasushi Hayakawa, Hiroyuki Nunogami, Takahiko Arakawa, Hisanori Hamano |
| 1998 | Low power logic synthesis under a general delay model. | Unni Narayanan, Peichen Pan, C. L. Liu |
| 1998 | Power-delay tradeoffs for radix-4 and radix-8 dividers. | Alberto Nannarelli, Toms Lang |
| 1998 | Power consumption of parallel spread spectrum correlator architectures. | Won Namgoong, Teresa H. Meng |
| 1998 | A delay distribution squeezing scheme with speed-adaptive threshold-voltage CMOS (SA-Vt CMOS) for low voltage LSIs. | Masayuki Miyazaki, Hiroyuki Mizuno, Koichiro Ishibashi |
| 1998 | Theoretical bounds for switching activity analysis in finite-state machines. | Diana Marculescu, Radu Marculescu, Massoud Pedram |
| 1998 | Stream synthesis for efficient power simulation based on spectral transforms. | Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi |
| 1998 | The petrol approach to high-level power estimation. | Rafael Peset Llopis, Kees Goossens |
| 1998 | CMOS front end components for micropower RF wireless systems. | Tsung-Hsien Lin, Henry Sanchez, Razieh Rofougaran, William J. Kaiser |
| 1998 | Low-energy embedded FPGA structures. | Eric Kusse, Jan M. Rabaey |
| 1998 | A 3.8-mW 2.5-GHz dual-modulus prescaler in a 0.8 m silicon bipolar production technology. | Herbert Knapp, Wilhelm Wilhelm, Mira Rest, Hans-Peter Trost |
| 1998 | True single-phase energy-recovering logic for low-power, high-speed VLSI. | Suhwan Kim, Marios C. Papaefthymiou |
| 1998 | Fast high-level power estimation for control-flow intensive design. | Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha |
| 1998 | The impact of data characteristics and hardware topology on hardware selection for low power DSP. | Gareth Keane, Jonathan R. Spanier, Roger F. Woods |
| 1998 | Estimation of maximum power supply noise for deep sub-micron designs. | Yi-Min Jiang, Kwang-Ting Cheng, An-Chang Deng |
| 1998 | Power dissipated by CMOS gates driving lossless transmission lines. | Yehea I. Ismail, Eby G. Friedman, Jos Luis Neves |
| 1998 | Voltage scheduling problem for dynamically variable voltage processors. | Tohru Ishihara, Hiroto Yasuura |
| 1998 | A power optimization method considering glitch reduction by gate sizing. | Masanori Hashimoto, Hidetoshi Onodera, Keikichi Tamaru |
| 1998 | Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors. | Nikolaos Bellas, Ibrahim N. Hajj, George D. Stamoulis, Constantine D. Polychronopoulos |
| 1998 | A high speed and low power SOL inverter using active body-bias. | Joonho Gil, Minkyu Je, Jongho Lee, Hyungcheol Shin |
| 1998 | An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. | Catherine H. Gebotys, Robert J. Gebotys |
| 1998 | Low power architecture of the soft-output Viterbi algorithm. | David Garrett, Mircea R. Stan |
| 1998 | 0.5V CMOS logic delivering 200 million 8*8 bit multiplications/s at less than 100 fj based on a 50nm T-gate SOI technology. | Volker Dudek, Reinhard Grube, Bernd Hfflinger, Michael Schau |
| 1998 | Power invariant vector compaction based on bit clustering and temporal partitioning. | Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano |