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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2000Application of deterministic logic BIST on industrial circuits.Gundolf Kiefer, Hans-Joachim Wunderlich, Harald P. E. Vranken, Erik Jan Marinissen
2000Multiple-parameter CMOS IC testing with increased sensitivity for I_DDQ.Ali Keshavarzi, Kaushik Roy, Charles F. Hawkins, Manoj Sachdev, Krishnamurthy Soumyanath, Vivek De
2000Programming of flash with ICT rights and responsibilities.Julia A. Keahey
2000A built-in self-repair analyzer (CRESTA) for embedded DRAMs.Tomoya Kawagoe, Jun Ohtani, Mitsutaka Niiro, Tukasa Ooishi, Mitsuhiro Hamada, Hideto Hidaka
2000Test response compaction by an accumulator behaving as a multiple input non-linear feedback shift register.Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos
2000A new paradigm in test for the next millennium.Jerry Katz, Rochit Rajsuman
2000Algorithm level re-computing with shifted operands-a register transfer level concurrent error detection technique.Ramesh Karri, Kaijie Wu
2000Power pin testing: making the test coverage complete.Frans G. M. de Jong, Ben Kup, Rodger Schuttert
2000Challenges of high supply currents during VLSI test.Gerald H. Johnson
2000Streamlining programmable device and system test using IEEE Std 1532.Neil G. Jacobson
2000Static property checking using ATPG vs. BDD techniques.Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng
2000Testing and characterization of the one-bit first-order delta-sigma modulator for on-chip analog signal analysis.Jiun-Lang Huang, Kwang-Ting Cheng
2000Microwave test mismatch and power de-embedding.Peter M. Higgins, Jim Lampos
2000A mixed mode BIST scheme based on reseeding of folding counters.Sybille Hellebrand, Hans-Joachim Wunderlich, Huaguo Liang
2000The implementation of IEEE Std 1149.1 boundary scan test strategy within a cellular infrastructure production environment.Stephen Harrison, Peter Collins, Greg Noeninckx
2000A stand-alone integrated test core for time and frequency domain measurements.Mohamed M. Hafed, Nazmy Abaskharoun, Gordon W. Roberts
2000Industrial evaluation of DRAM SIMM tests.Ad J. van de Goor, A. Paalvast
2000Test and on-line debug capabilities of IEEE Std 1149.1 in UltraSPARC-III microprocessor.Farideh Golshan
2000Low power BIST design by hypergraph partitioning: methodology and architectures.Patrick Girard, Christian Landrault, Los Guiller, Serge Pravossoudovitch
2000Test point insertion for compact test sets.M. J. Geuzebroek, J. Th. van der Linden, Ad J. van de Goor
2000Concurrent error detection in block ciphersSantiago Fernndez-Gomez, Juan J. Rodrguez-Andina, Enrique Mandado
2000Optical interferometric probing of advanced microprocessors.Travis M. Eiles, Keneth R. Wilsher, William K. Lo, G. Xiao
2000Enhanced DO-RE-ME based defect level prediction using defect site aggregation-MPG-D.Jennifer Dworak, Michael R. Grimaila, Sooryong Lee, Li-C. Wang, M. Ray Mercer
2000An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory.Dieu Van Dinh, Virginia Rabitoy
2000Universal test generation using fault tuples.Rao Desineni, Kumar N. Dwarakanath, Ronald D. Blanton
2,5262,550 of 4,920← PreviousNext →

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