Janusz Rajski
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
178
Venues
10
Active years
1985–2025
Best venue rank
A*
Where they publish
Papers
178 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ETS | Identification of Failing Flip-Flops with Triangular Test Response Compaction. | Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer |
| 2025 | ITC | Automated Selection of Optimal EDT Input Configuration. | Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer |
| 2025 | VTS | Timing-Verification Test Generation Targeting Small Delay Defects. | Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Kun-Han Tsai, Janusz Rajski |
| 2024 | ITC | Delay Monitoring Under Different PVT Corners for Test and Functional Operation. | Hari Addepalli, Jiezhong Wu, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2024 | ITC | Test Data Encryption with a New Stream Cipher. | Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak |
| 2024 | ITC | Deterministic In-Fleet Scan Test for a Cloud Computing Platform. | Dan Trock, Subramanian Mahadevan, Nilanjan Mukherjee, Lee Harrison, Janusz Rajski, Jerzy Tyszer |
| 2023 | ETS | Hybrid Ring Generators for In-System Test Applications. | Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak |
| 2022 | ETS | X-Masking for In-System Deterministic Test. | Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak |
| 2022 | ITC | Test Generation for an Iterative Design Flow with RTL Changes. | Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2022 | ITC | DIST: Deterministic In-System Test with X-masking. | Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak |
| 2022 | ITC | Hardware Root of Trust for SSN-basedDFT Ecosystems. | Janusz Rajski, Maciej Trawka, Jerzy Tyszer, Bartosz Wlodarczak |
| 2022 | VTS | Fast Test Generation for Structurally Similar Circuits. | Jerin Joe, Nilanjan Mukherjee, Irith Pomeranz, Janusz Rajski |
| 2022 | VTS | Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. | Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy |
| 2021 | ETS | Convolutional Compaction-Based MRAM Fault Diagnosis. | Bartosz Grzelak, Martin Keim, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2021 | ITC | On Reduction of Deterministic Test Pattern Sets. | Stephan Eggersgl, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer |
| 2020 | ETS | Test Sequence-Optimized BIST for Automotive Applications. | Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer |
| 2020 | ETS | Efficient Prognostication of Pattern Count with Different Input Compression Ratios. | Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski |
| 2020 | ITC | Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. | Jean-Franois Ct, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Coln-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant |
| 2020 | ITC | X-Tolerant Tunable Compactor for In-System Test. | Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak |
| 2020 | ITC | Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. | Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada |
| 2020 | VTS | Effective Design of Layout-Friendly EDT Decompressor. | Yu Huang, Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Jeffrey Mayer |
| 2019 | ITC | Test Time and Area Optimized BrST Scheme for Automotive ICs. | Nilanjan Mukherjee, Jerzy Tyszer, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki |
| 2019 | VTS | On Cyclic Scan Integrity Tests for EDT-based Compression. | Wu-Tung Cheng, Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer |
| 2018 | ITC | Hypercompression of Test Patterns. | Yu Huang, Sylwester Milewski, Janusz Rajski, Jerzy Tyszer, Chen Wang |
| 2018 | ITC | DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies. | Will Howell, Friedrich Hapke, Edward Brazil, Srikanth Venkataraman, R. Datta, Andreas Glowatz, Wilfried Redemund, J. Schmerberg, Anja Fast, Janusz Rajski |
| 2018 | ITC | Deterministic Stellar BIST for In-System Automotive Test. | Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer |
| 2018 | ITC | On New Class of Test Points and Their Applications. | Janusz Rajski, Jerzy Tyszer, Justyna Zawada |
| 2018 | VTS | Staggered ATPG with capture-per-cycle observation test points. | Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer |
| 2017 | ETS | ROM fault diagnosis for O(n | Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2017 | ITC | Full-scan LBIST with capture-per-cycle hybrid test points. | Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada |
| 2016 | ETS | Transistor stuck-on fault detection tests for digital CMOS circuits. | Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski |
| 2016 | ITC | Minimal area test points for deterministic patterns. | Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer |
| 2016 | ITC | Test point insertion in hybrid test compression/LBIST architectures. | Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada |
| 2016 | VLSID | Digital Testing of ICs for Automotive Applications. | Nilanjan Mukherjee, Janusz Rajski |
| 2015 | DAC | Design for low test pattern counts. | Haluk Konuk, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Deepak Solanki, Jerzy Tyszer, Justyna Zawada |
| 2015 | ITC | Embedded deterministic test points for compact cell-aware tests. | Cesar Acero, Derek Feltham, Friedrich Hapke, Elham K. Moghaddam, Nilanjan Mukherjee, Vidya Neerkundar, Marek Patyra, Janusz Rajski, Jerzy Tyszer, Justyna Zawada |
| 2015 | ITC | A deterministic BIST scheme based on EDT-compressed test patterns. | Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer |
| 2015 | VLSID | Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. | Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski |
| 2015 | VTS | Innovative practices session 11C: Advanced scan methodologies [3 presentations]. | Janusz Rajski, Nilanjan Mukherjee |
| 2014 | DAC | On Using Implied Values in EDT-based Test Compression. | Marcin Gebala, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2014 | DDECS | Quality assurance in memory built-in self-test tools. | Albert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada |
| 2014 | ETS | Cell-aware experiences in a high-quality automotive test suite. | Friedrich Hapke, Ralf Arnold, Matthias Beck, M. Baby, S. Straehle, J. F. Goncalves, A. Panait, R. Behr, Gwenol Maugard, A. Prashanthi, Juergen Schloeffel, Wilfried Redemund, Andreas Glowatz, Anja Fast, Janusz Rajski |
| 2014 | ETS | Using dynamic shift to reduce test data volume in high-compression designs. | Xijiang Lin, Mark Kassab, Janusz Rajski |
| 2014 | ITC | Isometric test compression with low toggling activity. | Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang |
| 2014 | VTS | Special session 8B - Panel: In-field testing of SoC devices: Which solutions by which players? | Jacob A. Abraham, Xinli Gu, Teresa MacLaurin, Janusz Rajski, Paul G. Ryan, Dimitris Gizopoulos, Matteo Sonza Reorda |
| 2013 | ETS | New test compression scheme based on low power BIST. | Jerzy Tyszer, Michal Filipek, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2013 | ITC | EDT bandwidth management - Practical scenarios for large SoC designs. | Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles |
| 2013 | ITC | On the generation of compact test sets. | Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang |
| 2013 | ITC | Fault diagnosis of TSV-based interconnects in 3-D stacked designs. | Janusz Rajski, Jerzy Tyszer |
| 2012 | ETS | Bandwidth-aware test compression logic for SoC designs. | Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski |
| 2012 | ITC | Low power test application with selective compaction in VLSI designs. | Dariusz Czysz, Janusz Rajski, Jerzy Tyszer |
| 2012 | ITC | Cell-aware Production test results from a 32-nm notebook processor. | Friedrich Hapke, Michael Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jrgen Schlffel, Janusz Rajski |
| 2012 | ITC | Low power programmable PRPG with enhanced fault coverage gradient. | Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2012 | VTS | Test generator with preselected toggling for low power built-in self-test. | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie |
| 2011 | ETS | Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. | Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer |
| 2011 | ETS | Reduced ATE Interface for High Test Data Compression. | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2011 | ITC | Cell-aware analysis for small-delay effects and production test results from different fault models. | Friedrich Hapke, Jrgen Schlffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers |
| 2011 | ITC | EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. | Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2011 | ITC | Low power compression utilizing clock-gating. | Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy |
| 2010 | ETS | Diagnosis of failing scan cells through orthogonal response compaction. | Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer |
| 2010 | ITC | Low power compression of incompatible test cubes. | Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer |
| 2010 | ITC | Dynamic channel allocation for higher EDT compression in SoC designs. | Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer |
| 2010 | ITC | Low capture power at-speed test in EDT environment. | Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab |
| 2010 | VTS | At-speed scan test with low switching activity. | Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab |
| 2009 | DATE | A scalable method for the generation of small test sets. | Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz |
| 2009 | ETS | We Have Got Compression, What Next? | Janusz Rajski |
| 2009 | ITC | Compression based on deterministic vector clustering of incompatible test cubes. | Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer |
| 2009 | ITC | Fault diagnosis for embedded read-only memories. | Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2009 | VLSID | High-Speed On-Chip Event Counters for Embedded Systems. | Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2009 | VLSID | Defect Aware to Power Conscious Tests - The New DFT Landscape. | Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2009 | VTS | Highly X-Tolerant Selective Compaction of Test Responses. | Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer |
| 2008 | ITC | Low Power Scan Shift and Capture in the EDT Environment. | Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
| 2008 | ITC | Test Generation for Interconnect Opens. | Xijiang Lin, Janusz Rajski |
| 2008 | ITC | High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. | Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2007 | DAC | Test Generation in the Presence of Timing Exceptions and Constraints. | Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski |
| 2007 | DAC | New Test Data Decompressor for Low Power Applications. | Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer |
| 2007 | DDECS | Logic Diagnosis and Yield Learning. | Janusz Rajski |
| 2007 | ETS | Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. | Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware |
| 2007 | VLSID | Low Shift and Capture Power Scan Tests. | Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2007 | VTS | Low Power Embedded Deterministic Test. | Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
| 2007 | VTS | Silicon Evaluation of Static Alternative Fault Models. | Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware |
| 2006 | DAC | A test pattern ordering algorithm for diagnosis with truncated fail data. | Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | DAC | Test response compactor with programmable selector. | Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
| 2006 | ETS | Convolutional Compactors with Variable Polynomials. | Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2006 | ETS | Enhancing Delay Fault Coverage through Low Power Segmented Scan. | Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi |
| 2006 | ITC | Diagnosis with Limited Failure Information. | Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen |
| 2006 | ITC | A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. | Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware |
| 2006 | ITC | Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. | Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
| 2006 | ITC | X-Press Compactor for 1000x Reduction of Test Data. | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab |
| 2006 | ITC | Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. | Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | VLSID | New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. | Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | VTS | The Impacts of Untestable Defects on Transition Fault Testing. | Xijiang Lin, Janusz Rajski |
| 2006 | VTS | Modular Compactor of Test Responses. | Wojciech Rajski, Janusz Rajski |
| 2006 | VTS | Scan Tests with Multiple Fault Activation Cycles for Delay Faults. | Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski |
| 2005 | ASPDAC | Propagation delay fault: a new fault model to test delay faults. | Xijiang Lin, Janusz Rajski |
| 2005 | DATE | Defect Aware Test Patterns. | Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz |
| 2005 | ETS | A unified fault model and test generation procedure for interconnect opens and bridges. | Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker |
| 2005 | ETS | Convolutional compaction-driven diagnosis of scan failures. | Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer, Chen Wang |
| 2005 | ITC | Compressed pattern diagnosis for scan chain failures. | Yu Huang, Wu-Tung Cheng, Janusz Rajski |
| 2005 | ITC | Diagnosis with convolutional compactors in presence of unknown states. | Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer |
| 2005 | ITC | Test compression - real issues and matching solutions. | Janusz Rajski |
| 2005 | VLSID | On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. | Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz |
| 2005 | VTS | Synthesis of X-Tolerant Convolutional Compactors. | Janusz Rajski, Jerzy Tyszer |
| 2004 | DATE | Nanometer Design: What are the Requirements for Manufacturing Test? | Janusz Rajski, Kan Thapar |
| 2004 | ICCD | Diagnosis of Hold Time Defects. | Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
| 2004 | ITC | Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. | Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski |
| 2004 | ITC | Realizing High Test Quality Goals with Smart Test Resource Usage. | Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski |
| 2004 | ITC | Fault Diagnosis in Designs with Convolutional Compactors. | Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski |
| 2004 | VLSID | Embedded Test for Low Cost Manufacturing. | Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht |
| 2004 | VTS | Planar High Performance Ring Generators. | Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 2003 | ICCAD | On Compacting Test Response Data Containing Unknown Values. | Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer |
| 2003 | ICCD | Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. | Janusz Rajski, Jerzy Tyszer |
| 2003 | ICCD | Multiple Fault Diagnosis Using n-Detection Tests. | Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski |
| 2003 | ITC | Impact of Multiple-Detect Test Patterns on Product Quality. | Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski |
| 2003 | ITC | Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. | Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski |
| 2003 | ITC | Test Challenges of Nanometer Technology. | Janusz Rajski |
| 2003 | ITC | Convolutional Compaction of Test Responses. | Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy |
| 2003 | ITC | An Efficient and Effective Methodology on the Multiple Fault Diagnosis. | Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski |
| 2003 | VTS | High Speed Ring Generators and Compactors of Test Data. | Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
| 2002 | DATE | Finding a Common Fault Response for Diagnosis during Silicon Debug. | Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy |
| 2002 | ICCAD | Conflict driven techniques for improving deterministic test pattern generation. | Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski |
| 2002 | ITC | Embedded Deterministic Test for Low-Cost Manufacturing Test. | Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian |
| 2002 | VLSID | Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. | Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski |
| 2002 | VTS | Innovations in Test Automation. | J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski |
| 2001 | ITC | Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. | John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly |
| 2001 | ITC | On static test compaction and test pattern ordering for scan designs. | Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy |
| 2001 | VTS | Enabling Embedded Memory Diagnosis via Test Response Compression. | John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare |
| 2000 | DAC | Self-test methodology for at-speed test of crosstalk in chip interconnects. | Xiaoliang Bai, Sujit Dey, Janusz Rajski |
| 2000 | ICCAD | Improving the Proportion of At-Speed Tests in Scan BIST. | Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski |
| 2000 | VTS | Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. | Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski |
| 1999 | ITC | Logic BIST for large industrial designs: real issues and case studies. | Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski |
| 1999 | ITC | Synthesis of pattern generators based on cellular automata with phase shifters. | Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski |
| 1999 | ITC | STAR-ATPG: a high speed test pattern generator for large scan designs. | Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska |
| 1999 | VLSID | Built-In Self-Test for Systems on Silicon. | Janusz Rajski, Jerzy Tyszer, Sanjay Patel |
| 1999 | VTS | Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. | Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer |
| 1998 | DAC | A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. | Aiman H. El-Maleh, Mark Kassab, Janusz Rajski |
| 1998 | ITC | Modular logic built-in self-test for IP cores. | Janusz Rajski, Jerzy Tyszer |
| 1998 | ITC | Automated synthesis of large phase shifters for built-in self-test. | Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer |
| 1998 | VTS | Design of Phase Shifters for BIST Applications. | Janusz Rajski, Jerzy Tyszer |
| 1997 | DAC | STARBIST: Scan Autocorrelated Random Pattern Generation. | Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska |
| 1997 | ITC | Parameterizable Testing Scheme for FIR Filters. | Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 1997 | ITC | Fault Diagnosis in Scan-Based BIST. | Janusz Rajski, Jerzy Tyszer |
| 1997 | ITC | Scan-Encoded Test Pattern Generation for BIST. | Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski |
| 1997 | VTS | Systems On Silicon: Design and Test Challenges. | J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian |
| 1996 | DATE | Multiplicative Window Generators of Pseudo-random Test Vectors. | Janusz Rajski, Jerzy Tyszer |
| 1996 | ITC | Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. | Nagesh Tamarapalli, Janusz Rajski |
| 1996 | ITC | Two-Dimensional Test Data Decompressor for Multiple Scan Designs. | Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski |
| 1996 | VTS | Hardware-Software Co-Design for Test: It's the Last Straw! | J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard |
| 1996 | VTS | A self-driven test structure for pseudorandom testing of non-scan sequential circuits. | Fidel Muradali, Janusz Rajski |
| 1995 | DAC | On Test Set Preservation of Retimed Circuits. | Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly |
| 1995 | DAC | Software Accelerated Functional Fault Simulation for Data-Path Architectures. | Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 1995 | DATE | Complexity of sequential ATPG. | Thomas E. Marchok, Aiman El-Maleh, Wojciech Maly, Janusz Rajski |
| 1995 | ICCAD | On testable multipliers for fixed-width data path architectures. | Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer |
| 1995 | ITC | Hierarchical Functional-Fault Simulation for High-Level Synthesis. | Mark Kassab, Janusz Rajski, Jerzy Tyszer |
| 1995 | VTS | Arithmetic built-in self test for high-level synthesis. | Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer |
| 1995 | VTS | Fault coverage analysis of RAM test algorithms. | Marc D. Riedel, Janusz Rajski |
| 1995 | VTS | Decompression of test data using variable-length seed LFSRs. | Nadime Zacharia, Janusz Rajski, Jerzy Tyszer |
| 1994 | ICCAD | Test pattern generation based on arithmetic operations. | Sanjay Gupta, Janusz Rajski, Jerzy Tyszer |
| 1994 | VTS | Delay-fault testability preservation of the concurrent decomposition and factorization transformations. | Aiman El-Maleh, Janusz Rajski |
| 1992 | ITC | Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. | Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski |
| 1992 | VTS | Recent advances in logic synthesis with testability. | Janusz Rajski, Jagadeesh Vasudevamurthy, Aiman El-Maleh |
| 1991 | DAC | Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. | Stephen Pateras, Janusz Rajski |
| 1991 | ITC | Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. | Stephen Pateras, Janusz Rajski |
| 1990 | ICCAD | On the Diagnostic Resolution of Signature Analysis. | Janusz Rajski, Jerzy Tyszer, Babak Salimi |
| 1990 | ICCAD | A Method for Concurrent Decomposition and Factorization of Boolean Expressions. | Jagadeesh Vasudevamurthy, Janusz Rajski |
| 1990 | ITC | The dynamic reduction of fault simulation. | Fadi Maamari, Janusz Rajski |
| 1990 | ITC | Empirical failure analysis and validation of fault models in CMOS VLSI. | Ashish Pancholy, Janusz Rajski, Larry J. McNaughton |
| 1990 | ITC | A method to calculate necessary assignments in algorithmic test pattern generation. | Janusz Rajski, Henry Cox |
| 1990 | ITC | Testability preserving transformations in multi-level logic synthesis. | Janusz Rajski, Jagadeesh Vasudevamurthy |
| 1989 | ITC | Testing of Glue Logic Interconnects Using Boundary Scan Architecture. | Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie |
| 1988 | ICCAD | Parallel PLA fault simulation based on Boolean vector operations. | Eli Chiprout, Janusz Rajski, Markus Robinson |
| 1988 | ICCAD | A fault simulation method based on stem regions. | Fadi Maamari, Janusz Rajski |
| 1988 | ICCD | A self-reconfiguration scheme for fault-tolerant VLSI processor arrays. | Stephen Pateras, Janusz Rajski |
| 1988 | ITC | On Multiple Fault Coverage and Aliasing Probability Measures. | Henry Cox, Andr Ivanov, Vinod K. Agarwal, Janusz Rajski |
| 1988 | ITC | Stuck-Open and Transition Fault Testing in CMOS Complex Gates. | Henry Cox, Janusz Rajski |
| 1988 | ITC | Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. | Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski |
| 1988 | ITC | An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. | Markus Robinson, Janusz Rajski |
| 1985 | ITC | Testing Properties and Applications of Inverter-Free PLA's. | Vinod K. Agarwal, Janusz Rajski |