| 2000 | Power conscious test synthesis and scheduling for BIST RTL data paths. | Nicola Nicolici, Bashir M. Al-Hashimi |
| 2000 | A comparison of classical scheduling approaches in power-constrained block-test scheduling. | Valentin Muresan, Xiaojun Wang, Valentina Muresan, Mircea Vladutiu |
| 2000 | Selection of potentially testable path delay faults for test generation. | Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy |
| 2000 | Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything? | Will R. Moore, Guido Gronthoud, Keith Baker, Maurice Lousberg |
| 2000 | Which concurrent error detection scheme to choose ? | Subhasish Mitra, Edward J. McCluskey |
| 2000 | Combinational logic synthesis for diversity in duplex systems. | Subhasish Mitra, Edward J. McCluskey |
| 2000 | On-the-shelf core pattern methodology for ColdFire(R) microprocessor cores. | Teresa L. McLaurin, John C. Potter |
| 2000 | The testability features of the MCF5407 containing the 4th generation ColdFire(R) microprocessor core. | Teresa L. McLaurin, Frank Frederick |
| 2000 | Stuck-fault tests vs. actual defects. | Edward J. McCluskey, Chao-Wen Tseng |
| 2000 | Motherboard testing using the PCI bus. | David McClintock, Lance Cunningham, Takis Petropoulos |
| 2000 | Deception by design: fooling ourselves with gate-level models. | Peter C. Maxwell, Jeff Rearick |
| 2000 | Current ratios: a self-scaling technique for production IDDQ testing. | Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman |
| 2000 | Comparing functional and structural tests. | Peter C. Maxwell, Ismed Hartanto, Lee Bentz |
| 2000 | Technique for testing a very high speed mixed signal read channel design. | Doug Matthes, John Ford |
| 2000 | Precise test generation for resistive bridging faults of CMOS combinational circuits. | Toshiyuki Maeda, Kozo Kinoshita |
| 2000 | Testing for tunneling opens. | Chien-Mo James Li, Edward J. McCluskey |
| 2000 | A good excuse for reuse: "open" TAP controller design. | David B. Lavo |
| 2000 | Using on-chip test pattern compression for full scan SoC designs. | Helmut Lang, Jens Pfeiffer, Jeff Maguire |
| 2000 | Test program synthesis for path delay faults in microprocessor cores. | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
| 2000 | Optimal analog trim techniques for improving the linearity of pipeline ADCs. | Turker Kuyel, Frank (Ching-Yuh) Tsay |
| 2000 | Identification of crosstalk switch failures in domino CMOS circuits. | Rahul Kundu, Ronald D. Blanton |
| 2000 | On invalidation mechanisms for non-robust delay tests. | Haluk Konuk |
| 2000 | Easy mixed signal test creation with test elements and procedures. | Andy Kittross |
| 2000 | Logic mapping on a microprocessor. | Anjali Kinra, Hari Balachandran, Regy Thomas, John Carulli |
| 2000 | An analysis of the delay defect detection capability of the ECR test method. | Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota |