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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2000Case-based reasoning: diagnosis of faults in complex systems through reuse of experience.L. Derere
2000Analysis of failure sources in surface-micromachined MEMS.Nilmoni Deb, Ronald D. Blanton
2000Reducing test data volume using external/LBIST hybrid test patterns.Debaleena Das, Nur A. Touba
2000Variance reduction using wafer patterns in I_ddQ data.W. Robert Daasch, James McNames, Daniel Bockelman, Kevin Cota
2000Hardware for production test of RFID interface embedded into chips for smart cards and labels used in contactless applications.Cristo da Costa
2000Test structure verification of logical BIST: problems and solutions.Michael Cogswell, Don Pearl, James Sage, Alan Troidl
2000Non-intrusive BIST for systems-on-a-chip.Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
2000Optimal INL/DNL testing of A/D converters using a linear model.Sasikumar Cherubal, Abhijit Chatterjee
2000Digital serial communication device testing and its implications on automatic test equipment architecture.Yongming Cai, T. P. Warwick, Sunil G. Rane, E. Masserrat
2000Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count.Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton
2000Reducing device yield fallout at wafer level test with electrohydrodynamic (EHD) cleaning.Jerry J. Broz, James C. Andersen, Reynaldo M. Rincon
2000Digital signature proposal for mixed-signal circuits.Anna Maria Brosa, Joan Figueras
2000BISTing data paths at behavioral level.David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre
2000A software development kit for dependable applications in embedded systems.Alfredo Benso, Silvia Chiusano, Paolo Prinetto
2000A programmable BIST architecture for clusters of multiple-port SRAMs.Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni
2000HDAlfredo Benso, Silvia Chiusano, Stefano Di Carlo, Paolo Prinetto, Fabio Ricciato, Maurizio Spadari, Yervant Zorian
2000Bridging the gap between embedded test and ATE.Martin Bell, Givargis Danialy, Michael C. Howells, Stephen Pateras
2000Deterministic partitioning techniques for fault diagnosis in scan-based BIST.Ismet Bayraktaroglu, Alex Orailoglu
2000Fault distinguishing pattern generation.Thomas Bartenstein
2000End-to-end testing for boards and systems using boundary scan.Robert W. Barr, Chen-Huan Chiang, Edward L. Wallace
2000DIST-based detection and diagnosis of multiple faults in FPGAs.Miron Abramovici, Charles E. Stroud
2000A framework to evaluate test tradeoffs in embedded core based systems-case study on TI's TMS320C27xx.Jais Abraham, Narayan Prasad, Srinivasa Chakravarthy B. S., Ameet Bagwe, Rubin A. Parekhji
2000Test generation for path-delay faults in one-dimensional iterative logic arrays.Nabil M. Abdulrazzaq, Sandeep K. Gupta
1999Towards a standard for embedded core test: an example.Yervant Zorian, Erik Jan Marinissen, Rohit Kapur, Tony Taylor, Lee Whetsel
1999Using LSSD to test modules at the board level.Thomas A. Ziaja
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