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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
1999Testing a system-on-a-chip with embedded microprocessor.Rochit Rajsuman
1999The HASS development process.David Rahe
1999Characterization and optimization of the production probing process.Minh Quach, Rich Samuelson, David Shaw
1999DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor.Carol Pyron, Mike Alexander, James Golab, George Joos, Bruce Long, Robert F. Molyneaux, Rajesh Raina, Nandu Tendolkar
1999Auto-calibrating analog timer for on-chip testing.Benoit Provost, Edgar Snchez-Sinencio
1999Applying lessons learned from TDDB testing.E. James Prendergast
1999On achieving complete coverage of delay faults in full scan circuits using locally available lines.Irith Pomeranz, Sudhakar M. Reddy
1999An efficient on-line-test and back-up scheme for embedded processors.Matthias Pflanz, Heinrich Theodor Vierhaus, F. Pompsch
1999High Time for Higher Level BIST.Christos A. Papachristou
1999Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment.Phil Nigh, David P. Vallett, Atul Patel, Jason Wright, Franco Motika, Donato O. Forlenza, Ray Kurtulik, Wendy Chong
1999Switch-level delay test.Suriyaprakash Natarajan, Sandeep K. Gupta, Melvin A. Breuer
1999Low overhead test point insertion for scan-based BIST.Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
1999Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm.Shigeru Nakahara, Keiichi Higeta, Masaki Kohno, Toshiaki Kawamura, Keizo Kakitani
1999An embedded technique for at-speed interconnect testing.Benoit Nadeau-Dostie, Jean-Francois Cote, Harry Hulvershorn, Stephen Pateras
1999Synthesis of pattern generators based on cellular automata with phase shifters.Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
1999DFT, DFY, and DFR; Which One(s) Do You Worry About?James A. Monzel
1999IAnthony C. Miller
1999A design diversity metric and reliability analysis for redundant systems.Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
1999Self-checking scheme for very fast clocks' skew correction.Cecilia Metra, Flavio Giovanelli, Mani Soma, Bruno Ricc
1999Current ratios: a self-scaling technique for production I_DDQ testing.Peter C. Maxwell, Pete O'Neill, Robert C. Aitken, Ronald Dudley, Neal Jaarsma, Minh Quach, Don Wiseman
1999Testing high speed high accuracy analog to digital converters embedded in systems on a chip.Solomon Max
1999Automatic timing margin failure location analysis by CycleStretch method.Mitsuo Matsumoto, Yoshiharu Ikeda
1999The evolution of a system test process [for Motorola GSM products].Simon Martin, Robert Bleck, Chryssa Dislis, Des Farren
1999Delay testing of SOI circuits: Challenges with the history effect.Eric W. MacDonald, Nur A. Touba
1999Is there a STIL for mixed signal testing?Marc Loranger
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