| 1999 | Expediting ramp-to-volume production. | Hari Balachandran, Jason Parker, Gordon Gammie, John W. Olson, Craig Force, Kenneth M. Butler, Sri Jandhyala |
| 1999 | SIA Roadmaps: Sunset Boulevard for l_DDQ. | Keith Baker |
| 1999 | Analog Fault Simulation: Need it? No. It is already done. | Eugene R. Atwood |
| 1999 | A method to improve the performance of high-speed waveform digitizing. | Koji Asami, Shinsuke Tajiri |
| 1999 | SCITT: Bringing DRAMs Into the Test Fold. | Frank W. Angelotti |
| 1999 | Scan Insertion at the Behavioral Level. | Chouki Aktouf |
| 1999 | Trends in SLI design and their effect on test. | Robert C. Aitken, Fidel Muradali |
| 1999 | It Makes Sense to Combine DFT and DFR/DFY. | Robert C. Aitken |
| 1999 | Limited access testing of analog circuits: handling tolerances. | Cherif Ahrikencheikh, Michael Spears |
| 1999 | Panel: Increasing test coverage in a VLSI desgin course. | Vishwani D. Agrawal |
| 1999 | Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. | Miron Abramovici, Charles E. Stroud, Carter Hamilton, Sajitha Wijesuriya, Vinay Verma |
| 1999 | Position Statement: Increasing Test Coverage in a VLSI Design Course. | Jacob A. Abraham |
| 1999 | Design-for-test methodology for Motorola PowerPC microprocessors. | Magdy S. Abadir, Rajesh Raina |
| 1998 | Testing embedded-core based system chips. | Yervant Zorian, Erik Jan Marinissen, Sujit Dey |
| 1998 | Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ. | Lan Zhao, D. M. H. Walker, Fabrizio Lombardi |
| 1998 | BETSY: synthesizing circuits for a specified BIST environment. | Zhe Zhao, Bahram Pouya, Nur A. Touba |
| 1998 | A new framework for generating optimal March tests for memory arrays. | Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty |
| 1998 | Triggering and clocking architecture for mixed signal test. | Naveed Zaman, Antony Spilman |
| 1998 | Defect-oriented testing of mixed-signal ICs: some industrial experience. | Y. Xing |
| 1998 | Defining ATPG rules checking in STIL. | Peter Wohl, John A. Waicukauski |
| 1998 | Extracting gate-level networks from simulation tables. | Peter Wohl, John A. Waicukauski |
| 1998 | A method of serial data jitter analysis using one-shot time interval measurements. | Jan B. Wilstrup |
| 1998 | Core test connectivity, communication, and control. | Lee Whetsel |
| 1998 | Functional ATE can meet the challenges. | Burnell G. West |
| 1998 | R-CBIST: an effective RAM-based input vector monitoring concurrent BIST technique. | Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantinos Halatsis |