| 1998 | Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment. | Phil Nigh, David P. Vallett, Atul Patel, Jason Wright |
| 1998 | SIA Roadmap: test must not limit future technologies. | Phil Nigh |
| 1998 | Design for soft-error robustness to rescue deep submicron scaling. | Michael Nicolaidis |
| 1998 | Scaling Deeper to Submicron: On-Line Testing to the Rescue. | Michael Nicolaidis |
| 1998 | High volume microprocessor test escapes, an analysis of defects our tests are missing. | Wayne M. Needham, Cheryl Prunty, Yeoh Eng Hong |
| 1998 | Just how real is the SIA roadmap. | Wayne M. Needham |
| 1998 | A BIST scheme for the detection of path-delay faults. | Nilanjan Mukherjee, Tapan J. Chakraborty, Sudipta Bhawmik |
| 1998 | On-line detection of logic errors due to crosstalk, delay, and transient faults. | Cecilia Metra, Michele Favalli, Bruno Ricc |
| 1998 | Contactless gigahertz testing. | Wolfgang Mertin, Anton Leyk, Ulf Behnke, Volker Wittpahl |
| 1998 | Limited access testing: IEEE 1149.4-instrumentation and methods. | John E. McDermid |
| 1998 | How we test Siemens Embedded DRAM Cores. | Roderick McConnell, Udo Mller, Detlev Richter |
| 1998 | Estimation of defect-free IDDQ in submicron circuits using switch level simulation. | Peter C. Maxwell, Jeff Rearick |
| 1998 | A structured and scalable mechanism for test access to embedded reusable cores. | Erik Jan Marinissen, Robert G. J. Arendsen, Gerard Bos, Hans Dingemanse, Maurice Lousberg, Clemens Wouters |
| 1998 | A test site thermal control system for at-speed manufacturing testing. | Mark Malinoski, James Maveety, Steve Knostman, Tom Jones |
| 1998 | DFT guidance through RTL test justification and propagation analysis. | Yiorgos Makris, Alex Orailoglu |
| 1998 | Cache RAM inductive fault analysis with fab defect modeling. | T. M. Mak, Debika Bhattacharya, Cheryl Prunty, Bob Roeder, Nermine Ramadan, F. Joel Ferguson, Jianlin Yu |
| 1998 | A layout-based approach for ordering scan chain flip-flops. | Samy Makar |
| 1998 | A goal tree based high-level test planning system for DSP real number models. | Morris Lin, James R. Armstrong, F. Gail Gray |
| 1998 | Probabilistic mixed-model fault diagnosis. | David B. Lavo, Brian Chess, Tracy Larrabee, Ismed Hartanto |
| 1998 | A performance analysis system for MEMS using automated imaging methods. | Glenn F. LaVigne, Sam L. Miller |
| 1998 | When two worlds merge [test issues for system-level ICs]. | Ken Lanier |
| 1998 | FakeFault: a silicon debug software tool for microprocessor embedded memory arrays. | Young-Jun Kwon, Ben Mathew, Hong Hao |
| 1998 | Microprocessor test and test tool methodology for the 500 MHz IBM S/390 G5 chip. | Mary P. Kusko, Bryan J. Robbins, Thomas J. Snethen, Peilin Song, Thomas G. Foote, William V. Huott |
| 1998 | GateMaker: a transistor to gate level model extractor for simulation, automatic test pattern generation and verification. | Sandip Kundu |
| 1998 | MEMS fault model generation using CARAMEL. | Abhijeet Kolpekwar, Chris S. Kellen, Ronald D. Blanton |