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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
1997Modifying User-Defined Logic for Test Access to Embedded Cores.Bahram Pouya, Nur A. Touba
1997Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data.James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan
1997Design, Fabrications and Use of Mixed-Signal IC Testability Structures.Kenneth P. Parker, John E. McDermid, Rodney A. Browen, Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa
1997Fault Macromodeling for Analog/Mixed-Signal Circuits.Chen-Yang Pan, Kwang-Ting Cheng
1997Unpowered Opens Test with X-Ray Laminography.Stig Oresjo
1997Testability Enhancement for Behavioral Descriptions Containing Conditional Statements.Kelly A. Ockunzzi, Christos A. Papachristou
1997Why Would an ASIC Foundry Accept Anything Less than Full Scan?Steven F. Oakland
1997So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment.Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken, Wojciech Maly
1997Application and Analysis of IDDQ Diagnostic Software.Phil Nigh, Donato O. Forlenza, Franco Motika
1997On-Line Testing for VLSI.Michael Nicolaidis
1997A Low-Cost Massively-Parallel Interconnect Test Method for MCM Substrates.K. E. Newman, David C. Keezer
1997An Efficient Scheme to Diagnose Scan Chains.Sridhar Narayanan, Ashutosh Das
1997Parameterizable Testing Scheme for FIR Filters.Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
1997An IDDQ Sensor Circuit for Low-Voltage ICs.Yukiya Miura
1997Scan Synthesis for One-Hot Signals.Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
1997On-Line Testing Scheme for Clock's Faults.Cecilia Metra, Michele Favalli, Bruno Ricc
1997Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique.Anne Meixner, Jash Banik
1997Incorporating Physical Design-for-Test into Routing.Richard McGowen, F. Joel Ferguson
1997RF Introduction and Analog Junction Techniques for Finding Opens.B. Karen McElfresh
1997Plug and Play or Plug and Pray: We Have a Right to Know It Will Work (Or Why It Won't).Colin M. Maunder
1997A Case Study of the Test Development for the 2nd Generation ColdFire Microprocessors.Michael Mateja, Alfred L. Crouch, Renny Eisele, Grady Giles, Dale Amason
1997Structuring STIL for Incremental Test Development.Gregory A. Maston
1997OLDEVDTP: A Novel Environment for Off-Line Debugging of VLSI Device Test Programs.Yuhai Ma, Wanchun Shi
1997Tree-Structured Linear Cellular Automata and Their Applications as PRPGs.J. Li, X. Sun, K. Soon
1997Efficient Identification of Non-Robustly Untestable Path Delay Faults.Zhongcheng Li, Robert K. Brayton, Yinghua Min
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