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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
1996Altering a Pseudo-Random Bit Sequence for Scan-Based BIST.Nur A. Touba, Edward J. McCluskey
1996Test Pattern Generation for Circuits with Asynchronous Signals Based on Scan.Mitsuo Teramoto, Tomoo Fukazawa
1996Opens Board Test Coverage: When is 99% Really 40%?Mick Tegethoff, Kenneth P. Parker, Ken Lee
1996Standard Test Interface Language (STIL): A New Language for Patterns and Waveforms.Anthony Taylor, Gregory A. Maston
1996Constructive Multi-Phase Test Point Insertion for Scan-Based BIST.Nagesh Tamarapalli, Janusz Rajski
1996Analog AC Harmonic Method for Detecting Solder Opens.Anthony J. Suto
1996Using ILA Testing for BIST in FPGAs.Charles E. Stroud, Eric Lee, Srinivasa Konala, Miron Abramovici
1996Cost Effective Frequency Measurement for Production Testing.Ralf Stoffels
1996Practical Issues of Failure Diagnosis and Analysis in a Fast Cycle Time Environment.Donald Staab
1996IC Failure Analysis Tools and Techniques - Macig, Mystery, and Science.Jerry M. Soden, Richard E. Anderson, Christopher L. Henderson
1996Synthesis-for-Initializability of Asynchronous Sequential Machines.Montek Singh, Steven M. Nowick
1996The Key to Concurrent Engineering is Design Tools.William R. Simpson
1996An Asynchronous Scan Path Concept for Micropipelines using the Bundled Data Convention.Volker Schber, Thomas Kiel
1996MCM Compute Node Thermal Failure - Design or Test Problem?Edward P. Sayre
1996Towards an Effective IJos van Sas, Urbain Swerts, Marc Darquennes
1996Optimal Multiple Chain Relay Testing Scheme for MCMs on Large Area Substrates.Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian
1996Four Multi Probing Test for 16 Bit DAC with Vertical Contact Probe Card.Seiji Sasho, Teruhisa Sakata
1996System Level Fault Simulation.Pablo Sanchez, Isabel Hidalgo
1996A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe
1996Deep Sub-micron IManoj Sachdev
1996A Method of Extending an 1149.1 Bus for Mixed-Signal Testing.Robert J. Russell
1996On Potential Fault Detection in Sequential Circuits.Elizabeth M. Rudnick, Janak H. Patel, Irith Pomeranz
1996Test Quality of Asynchronous Circuits: A Defect-oriented Evaluation.Marly Roncken, Eric Bruls
1996Optimal Scan for Pipelined Testing: An Asynchronous Foundation.Marly Roncken, Emile H. L. Aarts, Wim F. J. Verhaegh
1996Asynchronous Design: Working the Fast Lane.Marly Roncken
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