| 1996 | High Resolution I | Alan W. Righter, Jerry M. Soden, Richard W. Beegle |
| 1996 | Emerging Technologies Drive Domain-Specific Solutions. | Walden C. Rhines |
| 1996 | Challenge of the 90's: Testing CoreWare | Rochit Rajsuman |
| 1996 | Correlating Defects to Functional and I | Theo J. Powell, James R. Pair, Bernard G. Carbajal III |
| 1996 | A Unique Methodology for At-Speed Test of cDSP | David Potts, Roger Griesmer |
| 1996 | Generation of Test Cases for Hardware Design Verification of a Super-Scalar Fetch Processor. | Irith Pomeranz, Nirmal R. Saxena, Richard Reeve, Paritosh Kulkarni, Yan A. Li |
| 1996 | On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. | Irith Pomeranz, Sudhakar M. Reddy |
| 1996 | Digital Integrated Circuit Testing using Transient Signal Analysis. | James F. Plusquellic, Donald M. Chiarulli, Steven P. Levitan |
| 1996 | Commercial Design Verification: Methodology and Tools. | Carl Pixley, Noel R. Strader, William C. Bruce, Jaehong Park, Matt Kaufmann, Kurt Shultz, Michael Burns, Jainendra Kumar, Jun Yuan, Janet Nguyen |
| 1996 | Testability Features for a Submicron Voice-coder ASIC. | Francis Pichon |
| 1996 | SPC on the IC-Production Test Process. | Jos van der Peet, Ger van Boxem |
| 1996 | Introduction ITC 1996 Lecture Series on Unpowered Opens Testing. | Kenneth P. Parker |
| 1996 | Novel Optical Probing System with Submicron Spatial Resolution for Internal Diagnosis of VLSI Circuits. | Kazuyuki Ozaki, Hidenori Sekiguchi, Shinichi Wakana, Yoshiro Goto, Yasutoshi Umehara, Jun Matsumoto |
| 1996 | Scan Design Oriented Test Technique for VLSI's Using ATE. | Yasuji Oyama, Toshinobu Kanai, Hironobu Niijima |
| 1996 | Unpowered Opens Test with X-Ray Laminography. | Stig Oresjo |
| 1996 | A Universal Technique for Accelerating Simulation of Scan Test Patterns. | Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski |
| 1996 | Self-Learning Signature Analysis for Non-Volatile Memory Testing. | Piero Olivo, Marcello Dalpasso |
| 1996 | Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICs. | Thomas Olbrich, Jordi Prez, Ian Andrew Grout, Andrew Mark David Richardson, Carles Ferrer |
| 1996 | Realistic-Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits. | Michael J. Ohletz |
| 1996 | Orthogonal Scan: Low-Overhead Scan for Data Paths. | Robert B. Norwood, Edward J. McCluskey |
| 1996 | DFT Strategy for Intel Microprocessors. | Wayne M. Needham, Naga Gollakota |
| 1996 | A Unified Framework for Design Validation and Manufacturing Test. | Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote |
| 1996 | Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique. | Anne Meixner, Jash Banik |
| 1996 | I | Peter C. Maxwell, Robert C. Aitken, Kathleen R. Kollitz, Allen C. Brown |
| 1996 | Extending Calibration Intervals. | Solomon Max |