| 2020 | Flip-flops fanout splitting in scan designs. | Maxim Ladnushkin |
| 2020 | Cross-PUF Attacks on Arbiter-PUFs through their Power Side-Channel. | Trevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi |
| 2020 | Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven Learning. | Suhasini Komarraju, Abhijit Chatterjee |
| 2020 | Assuring Security and Reliability of Emerging Non-Volatile Memories. | Mohammad Nasim Imtiaz Khan, Swaroop Ghosh |
| 2020 | Hardware IP Protection Using Logic Encryption and Watermarking. | Rajit Karmakar, Santanu Chattopadhyay |
| 2020 | Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded Processor. | Vijay Kiran Kalyanam, Eric Mahurin, Michael Spence, Jacob A. Abraham |
| 2020 | Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel Computing. | Hiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto |
| 2020 | Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer Returns. | Hanbin Hu, Nguyen Nguyen, Chen He, Peng Li |
| 2020 | Knowledge Transfer for Diagnosis Outcome Preview with Limited Data. | Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton |
| 2020 | LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution. | Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton |
| 2020 | Logic Fault Diagnosis of Hidden Delay Defects. | Stefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen |
| 2020 | Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-In. | Chen He, Yanyao Yu |
| 2020 | Stress, Test, and Simulation of Analog IOs on Automotive ICs. | Chen He, Stephen Traynor, Gayathri Bhagavatheeswaran, Hector Sanchez |
| 2020 | At-speed DfT Architecture for Bundled-data Design. | Ricardo Aquino Guazzelli, Laurent Fesquet |
| 2020 | A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits Testing. | Vadim Geurkov, Lev Kirischian |
| 2020 | Modeling Accuracy of Wideband Power Amplifiers with Memory effects via Measurements. | Wei Gao, Tao Jing |
| 2020 | Automated Assertion Generation from Natural Language Specifications. | Steven J. Frederiksen, John Aromando, Michael S. Hsiao |
| 2020 | Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs. | Jean-Franois Ct, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Coln-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant |
| 2020 | A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. | Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang |
| 2020 | A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic Gates. | Sreeja Chowdhury, Rabin Yu Acharya, William Boullion, Andrew Felder, Mark Howard, Jia Di, Domenic Forte |
| 2020 | TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning. | Leon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee |
| 2020 | BISTLock: Efficient IP Piracy Protection using BIST. | Siyuan Chen, Jinwook Jung, Peilin Song, Krishnendu Chakrabarty, Gi-Joon Nam |
| 2020 | Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter. | Wei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang |
| 2020 | Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current Prediction. | Jun Chen, Masanori Hashimoto |
| 2020 | Functional Criticality Classification of Structural Faults in AI Accelerators. | Arjun Chaudhuri, Jonti Talukdar, Fei Su, Krishnendu Chakrabarty |