| 2025 | TIDE: Telemetry-Informed Delay Testing for Silent Data Corruption | Deepesh Sahoo, Eduardo Ortega, Peter Domanski, Farshad Firouzi, Krishnendu Chakrabarty |
| 2025 | MUX-based Polymorphic Registers and FSMs to Protect Roots of Trust from Voltage Fault Injection. | Sourav Roy, Domenic Forte |
| 2025 | Early Testing of Memory Redundant Row Elements. | Luc Romain, Roger Mah, Katarzyna Wojnowska, Albert Au, Lori Schramm |
| 2025 | Functional Logic Diagnosis with Observation Points on Next-State Variables. | Irith Pomeranz |
| 2025 | Full Enablement of Very-Low Voltage Testing to Deliver Zero Defect Quality Automotive Products. | Srimaiyee Pentyala, Stephen Traynor |
| 2025 | LITE: ATPG-Aware Lightweight Scan Instrumentation for Enhancing Test Efficiency. | Sudipta Paria, Md Rezoan Ferdous, Aritra Dasgupta, Atri Chatterjee, Swarup Bhunia |
| 2025 | LAMBDA: LLM-Assisted Malicious Bug Detection and Analysis in Hardware Designs. | Sudipta Paria |
| 2025 | OCTANE: On-Chip Telemetry-based Anomaly Notification Engine. | Eduardo Ortega, Arjun Hati, Jonti Talukdar, Woohyun Paik, Fei Su, Rita Chattopadhyay, Krishnendu Chakrabarty |
| 2025 | 'Shifting-left' Zero Defect Scan Test Development to Launch Automotive PPM-ready Products. | Ravi J. N, Stephen Traynor |
| 2025 | IC-PEPR: PEPR Testing Goes Intra-Cell. | Chris Nigh, Ruben Purdy, Wei Li, Subhasish Mitra, R. D. (Shawn) Blanton |
| 2025 | Sisyphus: Cross-Layer Efficiency Across NVM Technologies in Compute-in-Memory Architectures. | Ali Nezhadi, Odysseas Chatzopoulos, Mahta Mayahinia, George Papadimitriou, Mehdi Baradaran Tahoori, Dimitris Gizopoulos |
| 2025 | DRONE: Delay Defect and Marginality Targeted Scan Tests to Observe Insidious Errors. | Suriyaprakash Natarajan, Chaitali S. Oak, Nipun Chaplot, Vijay Kakollu, Venkata A. R. Gurram, Manish J. Mishra, Fayez Abu-gosh |
| 2025 | Automated Selection of Optimal EDT Input Configuration. | Grzegorz Mrugalski, Janusz Rajski, Maciej Trawka, Jerzy Tyszer |
| 2025 | Functional Test Generation for In-Field Testing of Deep Learning Models with Test Storage Constraints. | Dina A. Moussa, Michael Hefenbrock, Mehdi B. Tahoori |
| 2025 | Glitter PUF: A Passive Anti-Tamper PUF Based On Images Of Glitter Reflections. | Noel Moeskops, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil |
| 2025 | Pseudo-Random Low Power Built In Self Test. | Dale Meehl, Sameer Chillarige, Bharath Nandakumar, Carl Wisnesky, Krishna Chakravadhanula |
| 2025 | FPGA Synthesis of Arbitrary Jitter Injection for Multi-GHz Test Signals. | Shengbo Liu, Yindong Xiao, Cao Wang, Xiaochun Li, David C. Keezer |
| 2025 | Debugging and Preventing Abnormally High Vmin during Logic Scan Test Bring-up. | Min-Hsin Liu, Ding-Wei Cheng, James Chien-Mo Li, Chris Nigh, Szu Huat Goh, Mason Chern, Bing-Han Hsieh, Subhadip Kundu |
| 2025 | A Probabilistic Approach of Fault Propagation at RTL and its Application to Transient Fault Analysis. | Chien-Hsing Liang, Yu-Hong Chao, Jing-Jia Liou, Harry H. Chen |
| 2025 | Method for Diagnosing Clock Jitter Using FPGA. | Seongkwan Lee, Hyuntae Jeong, Cheolmin Park, Jun Yeon Won, Minho Kang, Jaemoo Choi |
| 2025 | IEA-Plugin: An AI Agent Reasoner for Test Data Analytics. | Seoyeon Kim, Yu Su, Li-C. Wang |
| 2025 | A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM. | Min-Kyu Kim, Incheol Nam, Minju Shin, Kyungrak Cho, Gijong Sung, Deasun Kim, Heeil Hong, SangJoon Hwang |
| 2025 | Exploiting the correlation with traditional fault models to speed-up cell-aware fault simulation. | Reza Khoshzaban, Iacopo Guglielminetti, Michelangelo Grosso, Matteo Sonza Reorda, Riccardo Cantoro |
| 2025 | High Reliability Delay-Based Weak FPGA PUF Using High-Resolution Stochastic Delay Measurement With Phase Locked Loops. | Kentaroh Katoh, Toru Nakura, Haruo Kobayashi |
| 2025 | An On-Chip Sensor For Online Monitoring of HCI-Induced Aging In Integrated Analog Circuits. | Saeid Karimpour, Emmanuel Nti Darko, Degang Chen |