| 2017 | An effective functional safety solution for automotive systems-on-chip. | Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian |
| 2017 | A/MS benchmark circuits for comparing fault simulation, DFT, and test generation methods. | Stephen Sunter, Peter Sarson |
| 2017 | Kernel based clustering for quality improvement and excursion detection. | Nik Sumikawa, Matt Nero, Li-C. Wang |
| 2017 | Exploiting path delay test generation to develop better TDF tests for small delay defects. | Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja |
| 2017 | DFM-aware fault model and ATPG for intra-cell and inter-cell defects. | Arani Sinha, Sujay Pandey, Ayush Singhal, Alodeep Sanyal, Alan Schmaltz |
| 2017 | Systematic defect detection methodology for volume diagnosis: A data mining perspective. | Chuanhe Jay Shan, Pietro Babighian, Yan Pan, John M. Carulli, Li-C. Wang |
| 2017 | Use models for extending IEEE 1687 to analog test. | Peter Sarson, Jeff Rearick |
| 2017 | Design-for-test and test time optimization for 3D SOCs. | Surajit Kumar Roy, Chandan Giri |
| 2017 | Analytical test of 3D integrated circuits. | Raphael Robertazzi, Micheal Scheurman, Matt Wordeman, Shurong Tian, Christy Tyberg |
| 2017 | Safety analysis for integrated circuits in the context of hybrid systems. | V. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur |
| 2017 | Demystifying automotive safety and security for semiconductor developer. | V. Prasanth, David Foley, Srivaths Ravi |
| 2017 | Frequency scaled segmented (FSS) scan architecture for optimized scan-shift power and faster test application time. | W. Pradeep, P. Narayanan, R. Mittal, N. Maheshwari, N. Naresh |
| 2017 | POSTT: Path-oriented static test compaction for transition faults in scan circuits. | Irith Pomeranz |
| 2017 | Selecting target bridging faults for uniform circuit coverage. | Irith Pomeranz |
| 2017 | RTL functional test generation using factored concolic execution. | Sonal Pinto, Michael S. Hsiao |
| 2017 | Marginal PCB assembly defect detection on DDR3/4 memory bus. | Sergei Odintsov, Artur Jutman, Sergei Devadze |
| 2017 | Hardware trojan detection through information flow security verification. | Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark Tehranipoor |
| 2017 | Full-scan LBIST with capture-per-cycle hybrid test points. | Sylwester Milewski, Nilanjan Mukherjee, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada |
| 2017 | Cognitive approach to support dynamic aging compensation. | Souhir Mhira, Vincent Huard, Ahmed Benhassain, Florian Cacho, David Meyer, Sylvie Naudet, Abhishek Jain, C. R. Parthasarathy, Alain Bravaix |
| 2017 | Security keynote: Ultra-low-energy security circuit primitives for IoT platforms. | Sanu Mathew |
| 2017 | Modeling trans-threshold correlations for reducing functional test time in ultra-low power systems. | Christopher J. Lukas, Farah B. Yahya, Benton H. Calhoun |
| 2017 | Front-end layout reflection for test chip design. | Zeye Liu, Phillip Fynan, Ronald D. Blanton |
| 2017 | Highly reliable and low-cost symbiotic IOT devices and systems. | Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen, Cheng-Wen Wu |
| 2017 | On applying scan based structural test for designs with dual-edge triggered flip-flops. | Xijiang Lin |
| 2017 | Single-pin test control for Big A, little D devices. | Michael Laisne, Hans Martin von Staudt, Sourabh Bhalerao, Mark Eason |