| 2013 | Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures. | Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jrg Henkel |
| 2013 | Best paper award winners. | Z. Yu, D. Chen |
| 2013 | A circular pipeline processing based deterministic parallel test pattern generator. | Kuen-Wei Yeh, Jiun-Lang Huang, Hao-Jan Chao, Laung-Terng Wang |
| 2013 | Diagnosis and Layout Aware (DLA) scan chain stitching. | Jing Ye, Yu Huang, Yu Hu, Wu-Tung Cheng, Ruifeng Guo, Liyang Lai, Ting-Pu Tai, Xiaowei Li, Wei-pin Changchien, Daw-Ming Lee, Ji-Jan Chen, Sandeep C. Eruvathi, Kartik K. Kumara, Charles C. C. Liu, Sam Pan |
| 2013 | A novel test structure for measuring the threshold voltage variance in MOSFETs. | Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada |
| 2013 | PADRE: Physically-Aware Diagnostic Resolution Enhancement. | Yang Xue, Osei Poku, Xin Li, Ronald D. Blanton |
| 2013 | Two-level compression through selective reseeding. | Peter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, Jonathon E. Colburn |
| 2013 | 30-Gb/s optical and electrical test solution for high-volume testing. | Daisuke Watanabe, Shin Masuda, Hideo Hara, Tsuyoshi Ataka, Atsushi Seki, Atsushi Ono, Toshiyuki Okayasu |
| 2013 | ATE test time reduction using asynchronous clock period. | Praveen Venkataramani, Vishwani D. Agrawal |
| 2013 | Design rule check on the clock gating logic for testability and beyond. | Kun-Han Tsai, Shuo Sheng |
| 2013 | AgentDiag: An agent-assisted diagnostic framework for board-level functional failures. | Zelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu |
| 2013 | A pattern mining framework for inter-wafer abnormality analysis. | Nik Sumikawa, Li-C. Wang, Magdy S. Abadir |
| 2013 | Accurate full spectrum test robust to simultaneous non-coherent sampling and amplitude clipping. | Siva Sudani, Li Xu, Degang Chen |
| 2013 | High sensitivity test signatures for unconventional analog circuit test paradigms. | Suraj Sindia, Vishwani D. Agrawal |
| 2013 | Early-life-failure detection using SAT-based ATPG. | Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker |
| 2013 | Welcome message. | Gordon W. Roberts, Rob Aitken |
| 2013 | Fault diagnosis of TSV-based interconnects in 3-D stacked designs. | Janusz Rajski, Jerzy Tyszer |
| 2013 | VLSI testing based security metric for IC camouflaging. | Jeyavijayan Rajendran, Ozgur Sinanoglu, Ramesh Karri |
| 2013 | Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults. | Mahesh Prabhu, Jacob A. Abraham |
| 2013 | Advanced method to refine waveform smeared by jitter in waveform sampler measurement. | Hideo Okawara |
| 2013 | SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. | Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai |
| 2013 | Zero-overhead self test and calibration of RF transceivers. | Afsaneh Nassery, Jae Woong Jeong, Sule Ozev |
| 2013 | Differential scan-path: A novel solution for secure design-for-testability. | Salvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl |
| 2013 | The implementation and application of a protocol aware architecture. | Timothy D. Lyons, George Conner, John Aslanian, Shawn Sullivan |
| 2013 | An enhanced procedure for calculating dynamic properties of high-performance DAC on ATE. | Ming Lu |