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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2012"Managing process variance in analog designs".Eugene R. Atwood
2012DC temperature measurements for power gain monitoring in RF power amplifiers.Josep Altet, Diego Mateo, Didac Gmez, Xavier Perpi, Miquel Vellveh, Xavier Jord
2012FPGA-based synthetic instrumentation for board test.Igor Aleksejev, Artur Jutman, Sergei Devadze, Sergei Odintsov, Thomas Wenzel
2012A dynamic programming solution for optimizing test delivery in multicore SOCs.Mukesh Agrawal, Michael Richter, Krishnendu Chakrabarty
2012Experiences with non-intrusive sensors for RF built-in test.Louay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Christophe Kelma
2011Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks.Zhaobo Zhang, Krishnendu Chakrabarty, Zhanglei Wang, Zhiyuan Wang, Xinli Gu
2011Challenges and best practices in advanced silicon debug.Jing Zeng
2011Faster-than-at-speed test for increased test quality and in-field reliability.Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara
2011Adaptive multidimensional outlier analysis for analog and mixed signal circuits.Ender Yilmaz, Sule Ozev, Kenneth M. Butler
2011Online timing variation tolerance for digital integrated circuits.Guihai Yan, Xiaowei Li
2011A novel scan segmentation design method for avoiding shift timing failure in scan testing.Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang
2011Application of a continuous-time level crossing quantization method for timing noise measurements.Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu
2011Test clock domain optimization for peak power supply noise reduction during scan.Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li
2011Lithography aware critical area estimation and yield analysis.Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu
2011A Software-Based Self-Test methodology for on-line testing of processor caches.George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos
2011Physically-aware analysis of systematic defects in integrated circuits.Wing Chiu Tam, R. D. (Shawn) Blanton
2011Actual implementation of multi domain test: Further reduction of cost of test.Yasuhiro Takahashi, Akinori Maeda, Mitsuhiro Ogura
2011Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan.Stephen K. Sunter, Aubin Roy
2011Forward prediction based on wafer sort data - A case study.Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir
2011A novel robust and accurate spectral testing method for non-coherent sampling.Siva Sudani, Minshun Wu, Degang Chen
2011Evaluation of TSV and micro-bump probing for wide I/O testing.Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel
2011A systems perspective on the R&D of industrial technology.Jyuo-Min Shyu
2011Partial state monitoring for fault detection estimation.Yiwen Shi, Kantapon Kaewtip, Wan-Chan Hu, Jennifer Dworak
2011A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores.Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab
2011End-to-end error correction and online diagnosis for on-chip networks.Saeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng
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