| 2011 | Low power compression utilizing clock-gating. | Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy |
| 2011 | Surviving state disruptions caused by test: A case study. | Kenneth P. Parker, Shuichi Kameyama, David Dubberke |
| 2011 | Hardware hooks for transition scan characterization. | Pankaj Pant, Eric Skeels |
| 2011 | Elegant construction of SSC implemented signal by AWG and organized under-sampling of wideband signal. | Hideo Okawara |
| 2011 | Pre-bond probing of TSVs in 3D stacked ICs. | Brandon Noia, Krishnendu Chakrabarty |
| 2011 | Industry leaders panel - How will testing change in the next 10 years? | Phil Nigh |
| 2011 | P-PET: Partial pseudo-exhaustive test for high defect coverage. | Abdullah Mumtaz, Michael E. Imhof, Hans-Joachim Wunderlich |
| 2011 | Development of an ATE test cell for at-speed characterization and production testing. | Jose Moreira |
| 2011 | DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. | Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji |
| 2011 | Multi-function multi-GHz ATE extension using state-of-the-art FPGAs. | A. M. Majid, David C. Keezer |
| 2011 | Analyzing ATE interconnect performance for serial links of 10 Gbps and above. | Mitchell Lin, Tyler Tolman |
| 2011 | Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. | Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen |
| 2011 | Deterministic IDDQ diagnosis using a net activation based model. | Andras Kun, Ralf Arnold, Peter Heinrich, Gwenol Maugard, Huaxing Tang, Wu-Tung Cheng |
| 2011 | Defect Oriented Testing for analog/mixed-signal devices. | Bram Kruseman, Bratislav Tasic, Camelia Hora, Jos Dohmen, Hamidreza Hashempour, Maikel van Beurden, Yizi Xing |
| 2011 | Multi-site test of RF transceivers on low-cost digital ATE. | Ivo Koren, Ben Schuffenhauer, Frank Demmerle, Frank Neugebauer, Gert Pfahl, Dirk Rautmann |
| 2011 | EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. | Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski |
| 2011 | Real-time testing method for 16 Gbps 4-PAM signal interface. | Masahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu |
| 2011 | Investigation into voltage and process variation-aware manufacturing test. | Urban Ingelsson, Bashir M. Al-Hashimi |
| 2011 | Cell-aware analysis for small-delay effects and production test results from different fault models. | Friedrich Hapke, Jrgen Schlffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, Michael Reese, J. Rearick, Jason Rivers |
| 2011 | The gap: Test challenges in Asia manufacturing field. | Xinli Gu |
| 2011 | Die-level adaptive test: Real-time test reordering and elimination. | Kapil R. Gotkhindikar, W. Robert Daasch, Kenneth M. Butler, John M. Carulli Jr., Amit Nahar |
| 2011 | Generic, orthogonal and low-cost March Element based memory BIST. | Ad J. van de Goor, Said Hamdioui, Halil Kukner |
| 2011 | Using well/substrate bias manipulation to enhance voltage-test-based defect detection. | Anne E. Gattiker, Phil Nigh |
| 2011 | On using address scrambling to implement defect tolerance in SRAMs. | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
| 2011 | IEEE Std 1581 - A standardized test access methodology for memory devices. | Heiko Ehrenberg, Bob Russell |