| 2011 | Wafer probe test cost reduction of an RF/A device by automatic testset minimization - A case study. | Dragoljub Gagi Drmanac, Michael Laisne |
| 2011 | Techniques to improve memory interface test quality for complex SoCs. | V. R. Devanathan, Srinivas Kumar Vooka |
| 2011 | Power, programmability, and granularity: The challenges of ExaScale computing. | Bill Dally |
| 2011 | Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. | Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu |
| 2011 | Transition test bring-up and diagnosis on UltraSPARC | Liang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson |
| 2011 | Design-for-debug layout adjustment for FIB probing and circuit editing. | Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen |
| 2011 | A fully cell-based design for timing measurement of memory. | Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao |
| 2011 | Test cost reduction through performance prediction using virtual probe. | Hsiu-Ming Chang, Kwang-Ting Cheng, Wangyang Zhang, Xin Li, Kenneth M. Butler |
| 2011 | Optimal manufacturing flow to determine minumum operating voltage. | Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas |
| 2011 | Test access and the testability features of the Poulson multi-core Intel Itanium processor. | Dilip K. Bhavsar, Steve Poehlman |
| 2011 | Efficient combination of trace and scan signals for post silicon validation and debug. | Kanad Basu, Prabhat Mishra, Priyadarsan Patra |
| 2011 | Accurate signature driven power conscious tuning of RF systems using hierarchical performance models. | Aritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee |
| 2011 | In circuit test (ICT): The king is dead; long live the king! | Bailarico Balangue |
| 2011 | State of the art low capture power methodology. | Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto |
| 2011 | Logic BIST silicon debug and volume diagnosis methodology. | M. Enamul Amyeen, Andal Jayalakshmi, Srikanth Venkataraman, Sundar V. Pathy, Ewe C. Tan |
| 2011 | Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current. | Dhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson |
| 2010 | Board-level fault diagnosis using an error-flow dictionary. | Zhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty |
| 2010 | A diagnostic test generation system. | Yu Zhang, Vishwani D. Agrawal |
| 2010 | Estimating defect-type distributions through volume diagnosis and defect behavior attribution. | Xiaochun Yu, Ronald D. Blanton |
| 2010 | The scan-DFT features of AMD's next-generation microprocessor core. | Mahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen |
| 2010 | Adaptive test flow for mixed-signal/RF circuits using learned information from device under test. | Ender Yilmaz, Sule Ozev, Kenneth M. Butler |
| 2010 | Testing of latch based embedded arrays using scan tests. | Fan Yang, Sreejit Chakravarty |
| 2010 | Is test power reduction through X-filling good enough? | Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed |
| 2010 | Increasing PRPG-based compression by delayed justification. | Peter Wohl, John A. Waicukauski, T. Finklea |
| 2010 | Commanded Test Access Port operations. | Lee Whetsel |