| 2010 | Concurrent test planning. | Bethany Van Wagenen, Edward Seng |
| 2010 | Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. | Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab |
| 2010 | Test cycle power optimization for scan-based designs. | Kun-Han Tsai, Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli |
| 2010 | Detecting and diagnosing open defects. | Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson |
| 2010 | Parity prediction synthesis for nano-electronic gate designs. | D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich |
| 2010 | Vendor-agnostic native compression engine. | Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday |
| 2010 | On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs. | Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen |
| 2010 | Systematic defect identification through layout snippet clustering. | Wing Chiu Tam, Osei Poku, Ronald D. Blanton |
| 2010 | DFM aware bridge pair extraction for manufacturing test development. | Sarveswara Tammali, Vishal Khatri, Gowrysankar Shanmugam, Mark Terry |
| 2010 | BIST of I/O circuit parameters via standard boundary scan. | Stephen K. Sunter, Matthias Tilmann |
| 2010 | A novel approach to improve test coverage of BSR cells. | Ankush Srivastava, Ajay Prajapati, Vinay Soni |
| 2010 | AXIe 2.0 and MVP-C: Open ATE software standards. | Kenneth Spargo |
| 2010 | On techniques for handling soft errors in digital circuits. | Warin Sootkaneung, Kewal K. Saluja |
| 2010 | Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packages. | Ki-Jae Song, Hunkyo Seo, Sang-hyun Ko |
| 2010 | Methodology for early and accurate test power estimation at RTL. | Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe |
| 2010 | Predictive analysis for projecting test compression levels. | Ozgur Sinanoglu, Sobeeh Almukhaizim |
| 2010 | Error-locality-aware linear coding to correct multi-bit upsets in SRAMs. | Saeed Shamshiri, Kwang-Ting Cheng |
| 2010 | RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage. | Alodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara |
| 2010 | Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. | Rance Rodrigues, Sandip Kundu, Omer Khan |
| 2010 | New tools and methodology for advanced parametric and defect structure test. | Raphael Robertazzi, Louis Medina, Ernesto Shiling, Garry Moore, Ronald Geiger, Jiun-Hsin Liao, John Williamson |
| 2010 | Characterizing mechanical performance of Board Level Interconnects for In-Circuit Test. | Rosa D. Reinosa, Aileen Allen, Elizabeth Benedetto, Alan Mcallister |
| 2010 | Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. | Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran |
| 2010 | Scan chain securization though Open-Circuit Deadlocks. | Michele Portolan, Bradford G. Van Treuren, Suresh Goyal |
| 2010 | Surviving state disruptions caused by test: The "Lobotomy Problem". | Kenneth P. Parker |
| 2010 | Lessons from at-speed scan deployment on an Intel Itanium microprocessor. | Pankaj Pant, Joshua Zelman, Glenn Coln-Bonet, Jennifer Flint, Steve Yurash |