IEEE International Test Conference
ITC
A
CORE rank
CORE rank (raw)
A
Fields of research
Computer Systems Engineering
Papers indexed
4,920
1981–2025
Papers per year
1981207 peak2025
Most published authors
ITC papers
4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.
| Year | Title | Authors |
|---|---|---|
| 2010 | STIL P1450.4: A standard for test flow specification. | Jim O'Reilly, Ajay Khoche, Ernst Wahl, Bruce R. Parnas |
| 2010 | Constrained ATPG for functional RTL circuits using F-Scan. | Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara |
| 2010 | A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation. | Shuou Nomura, Karthikeyan Sankaralingam, Ranganathan Sankaralingam |
| 2010 | Optimization methods for post-bond die-internal/external testing in 3D stacked ICs. | Brandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen |
| 2010 | Automatic classification of bridge defects. | Jeffrey E. Nelson, Wing Chiu Tam, Ronald D. Blanton |
| 2010 | Path coverage based functional test generation for processor marginality validation. | Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche |
| 2010 | Synthetic DSP approach for novel FPGA-based measurement of error vector magnitude. | Devin Morris, William R. Eisenstadt, Andrea Paganini, Mustapha Slamani, Timothy Platt, John Ferrario |
| 2010 | Low capture power at-speed test in EDT environment. | Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab |
| 2010 | Structural approach for built-in tests in RF devices. | Deepa Mannath, Dallas Webster, Victor Montao-Martinez, David Cohen, Shai Kush, Ganesan Thiagarajan, Adesh Sontakke |
| 2010 | Analog neural network design for RF built-in self-test. | Dzmitry Maliuk, Haralampos-G. D. Stratigopoulos, He Huang, Yiorgos Makris |
| 2010 | Rapid FPGA delay characterization using clock synthesis and sparse sampling. | Mehrdad Majzoobi, Eva L. Dyer, Ahmed Elnably, Farinaz Koushanfar |
| 2010 | Complete testing of receiver jitter tolerance. | Timothy D. Lyons |
| 2010 | Mask versus Schematic - an enhanced design-verification flow for first silicon success. | Tseng-Chin Luo, Eric Leong, Mango Chia-Tso Chao, Philip A. Fisher, Wen-Hsiang Chang |
| 2010 | nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applications. | Huawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li |
| 2010 | Fault models and test methods for subthreshold SRAMs. | Chen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang |
| 2010 | A practical scan re-use scheme for system test. | Kelly Lee |
| 2010 | Post-production performance calibration in analog/RF devices. | Nathan Kupp, He Huang, Petros Drineas, Yiorgos Makris |
| 2010 | Automated trace signals selection using the RTL descriptions. | Ho Fai Ko, Nicola Nicolici |
| 2010 | A high linearity compact timing vernier for CMOS timing generator. | Jun Kohno, Tatsuro Akiyama, Dai Kato, Makoto Imamura |
| 2010 | System reliability evaluation using concurrent multi-level simulation of structural faults. | Michael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto |
| 2010 | Experiences with parametric BIST for production testing PLLs with picosecond precision. | Rakesh Kinger, Swetha Narasimhawsamy, Stephen K. Sunter |
| 2010 | A high density small size RF test module for high throughput multiple resource testing. | Masayuki Kimishima, S. Mizuno, T. Seki, H. Takeuti, Haruki Nagami, Hideki Shirasu, Y. Haraguti, J. Okayasu, M. Nakanishi |
| 2010 | Modeling the impact of process variation on resistive bridge defects. | S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu |
| 2010 | Low cost at-speed testing using On-Product Clock Generation compatible with test compression. | Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise |
| 2010 | ADC linearity testing method with single analog monitoring port. | Tomohiro Kawachi, Koichi Irie |
1,026–1,050 of 4,920← PreviousNext →
Comparable venues
Other A*/A conferences filed under the same field of research.
- ADATEDesign, Automation and Test in Europe Conference
- A*DACDesign Automation Conf
- ASCInternational Conference for High Performance Computing, Networking, Storage and Analysis (was Supercomputing Conference)
- AICCADIEEE/ACM International Conference on Computer-Aided Design
- A*ISCAACM International Symposium on Computer Architecture
- A*MICROInternational Symposium on Microarchitecture
- AISLPEDIEEE/ACM International Symposium on Low Power Electronics and Design
- AICSACM International Conference on Supercomputing