| 2009 | A robust method for identifying a deterministic jitter model in a total jitter distribution. | Takahiro J. Yamaguchi, Kiyotaka Ichiyama, X. H. Hou, Masahiro Ishida |
| 2009 | Low power multi-chains encoding scheme for SoC in low-cost environment. | Po-Han Wu, Jiann-Chyi Rau |
| 2009 | A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design. | Hsiang-Huang Wu, Jih-Nung Lee, Ming-Cheng Chiang, Po-Wei Liu, Chi-Feng Wu |
| 2009 | A novel architecture for on-chip path delay measurement. | Xiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta |
| 2009 | High Speed I/O Test Cable Assembly Interfaces for Next Generation Multi-Gigabit Serial Protocols. | Jim Vana, Alexander Barr, Richard Scherer, Abhay Joshi |
| 2009 | Portable simulation/emulation stimulus on an industrial-strength SoC. | Francisco Torres, Rohit Srivastava, Javier Ruiz, Charles H.-P. Wen, Mrinal Bose, Jayanta Bhadra |
| 2009 | BIST scheme for RF VCOs allowing the self-correction of the cut. | Luca Testa, Herv Lapuyade, Yann Deval, Olivier Mazouffre, Jean-Louis Carbonro, Jean-Baptiste Bgueret |
| 2009 | Augmenting board test coverage with new intel powered opens boundary scan instruction. | Chwee Liong Tee, Tzyy Haw Tan, Chin Chuan Ng |
| 2009 | AutoRex: An automated post-silicon clock tuning tool. | Desta Tadesse, Joel Grodstein, R. Iris Bahar |
| 2009 | Testing bridges to nowhere - combining Boundary Scan and capacitive sensing. | Steve Sunter, Kenneth P. Parker |
| 2009 | On-chip power supply noise measurement using Time Resolved Emission (TRE) waveforms of Light Emission from Off-State Leakage Current (LEOSLC). | Franco Stellari, Peilin Song, John Sylvestri, D. Miles, Orazio P. Forlenza, Donato O. Forlenza |
| 2009 | X-alignment techniques for improving the observability of response compactors. | Ozgur Sinanoglu, Sobeeh Almukhaizim |
| 2009 | Thermal characterization of BIST, scan design and sequential test methodologies. | Muzaffer O. Simsir, Niraj K. Jha |
| 2009 | Design-for-secure-test for crypto cores. | Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki |
| 2009 | New modeling methods for bounded Gaussian jitter (BGJ)/noise (BGN) and their applications in jitter/noise estimation/testing. | Masashi Shimanouchi, Mike Peng Li, Daniel Chow |
| 2009 | Very-Low-Voltage testing of amorphous silicon TFT circuits. | Shiue-Tsung Shen, Wei-Hsiao Liu, Chien-Mo James Li, I-Chun Cheng |
| 2009 | Low cost AM/AM and AM/PM distortion measurement using distortion-to-amplitude transformations. | Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee |
| 2009 | Low cost test point insertion without using extra registers for high performance design. | Haoxing Ren, Mary P. Kusko, Victor N. Kravets, Rona Yaari |
| 2009 | IEEE P1687 IJTAG a presentation of current technology. | Ken Posse, Al Crouch, Jeff Rearick |
| 2009 | Scalable and efficient integrated test architecture. | Michele Portolan, Suresh Goyal, Bradford G. Van Treuren |
| 2009 | Voltage transient detection and induction for debug and test. | Rex Petersen, Pankaj Pant, Pablo Lopez, Aaron Barton, Jim Ignowski, Doug Josephson |
| 2009 | What is IEEE P1149.8.1 and why? | Kenneth P. Parker, Jeff Burgess |
| 2009 | SSC applied serial ATA signal generation and analysis by analog tester resources. | Hideo Okawara |
| 2009 | Design for failure analysis inserting replacement-type observation points for LVP. | Junpei Nonaka, Toshio Ishiyama, Kazuki Shigeta |
| 2009 | Intel | Jay J. Nejedlo, Rahul Khanna |