| 2008 | Finding Power/Ground Defects on Connectors - Case Study. | Steve Hird, Reggie Weng |
| 2008 | Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model. | Stefan Hillebrecht, Ilia Polian, Piet Engelke, Bernd Becker, Martin Keim, Wu-Tung Cheng |
| 2008 | Detection and Diagnosis of Static Scan Cell Internal Defect. | Ruifeng Guo, Liyang Lai, Yu Huang, Wu-Tung Cheng |
| 2008 | A High-Speed Structural Method for Testing Address Decoder Faults in Flash Memories. | Olivier Ginez, Jean-Michel Portal, Hassen Aziza |
| 2008 | Test Access Mechanism for Multiple Identical Cores. | Grady Giles, Jing Wang, Anuja Sehgal, Kedarnath J. Balakrishnan, James Wingfield |
| 2008 | Integration of Hardware Assertions in Systems-on-Chip. | Jeroen Geuzebroek, Bart Vermeulen |
| 2008 | Unraveling Variability for Process/Product Improvement. | Anne Gattiker |
| 2008 | Low cost testing of multi-GBit device pins with ATE assisted loopback instrument. | William Fritzsche, Asim E. Haque |
| 2008 | On-chip Timing Uncertainty Measurements on IBM Microprocessors. | Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem |
| 2008 | Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality. | Stefan Eichenberger, Jeroen Geuzebroek, Camelia Hora, Bram Kruseman, Ananta K. Majhi |
| 2008 | IEEE P1581 drastically simplifies connectivity test for memory devices. | Heiko Ehrenberg |
| 2008 | DFT Implementationis for Striking the Right Balance between Test Cost and Test Quality for Automotive SOCs. | Amit Dutta, Srinivasulu Alampally, V. Prasanth, Rubin A. Parekhji |
| 2008 | Solving In-Circuit Defect Coverage Holes with a Novel Boundary Scan Application. | Dave F. Dubberke, James J. Grealish, Bill Van Dick |
| 2008 | High Test Quality in Low Pin Count Applications. | Jayant D'Souza, Subramanian Mahadevan, Nilanjan Mukherjee, Graham Rhodes, Jocelyn Moreau, Thomas Droniou, Paul Armagnat, Damien Sartoretti |
| 2008 | The Advantages of Limiting P1687 to a Restricted Subset. | Jason Doege, Alfred L. Crouch |
| 2008 | Justifying DFT with a Hierarchical Top-Down Cost-Benefit Model. | Scott Davidson |
| 2008 | Low Power Scan Shift and Capture in the EDT Environment. | Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer |
| 2008 | Solder Bead on High Density Interconnect Printed Circuit Board. | Brandon Chu |
| 2008 | IEEE 1500 Compatible Secure Test Wrapper For Embedded IP Cores. | Geng-Ming Chiu, James Chien-Mo Li |
| 2008 | A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs. | Vivek Chickermane, Patrick R. Gallagher Jr., James Sage, Paul Yuan, Krishna Chakravadhanula |
| 2008 | Transition Test on UltraSPARC- T2 Microprocessor. | Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen |
| 2008 | Test Quality Improvement with Timing-aware ATPG: Screening small delay defect case study. | Che-Jen Jerry Chang, Takeo Kobayashi |
| 2008 | Testing Methodology of Embedded DRAMs. | Chi-Min Chang, Mango Chia-Tso Chao, Rei-Fu Huang, Ding-Yuan Chen |
| 2008 | On-line Failure Detection in Memory Order Buffers. | Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella |
| 2008 | Modeling Test Escape Rate as a Function of Multiple Coverages. | Kenneth M. Butler, John M. Carulli Jr., Jayashree Saxena |