| 2007 | On the saturation of n-detection test sets with increased n. | Irith Pomeranz, Sudhakar M. Reddy |
| 2007 | Delay defect diagnosis using segment network faults. | Osei Poku, Ronald D. Blanton |
| 2007 | Finding power/ground defects on connectors - a new approach. | Kenneth P. Parker, Stephen Hird |
| 2007 | A bead probe CAD strategy for in-circuit test. | Kenneth P. Parker, Don DeMille |
| 2007 | Mining-guided state justification with partitioned navigation tracks. | Ankur Parikh, Weixin Wu, Michael S. Hsiao |
| 2007 | Statistical test: A new paradigm to improve test effectiveness & efficiency. | Peter M. O'Neill |
| 2007 | Gate delay ratio model for unified path delay analysis. | Yukio Okuda |
| 2007 | Real-time signal processing - a new PLL test approach. | Hideo Okawara |
| 2007 | GRAAL: a new fault tolerant design paradigm for mitigating the flaws of deep nanometric technologies. | Michael Nicolaidis |
| 2007 | Rapid UHF RFID silicon debug and production testing. | Udaya Shankar Natarajan, Hemalatha Shanmugasundaram, Prachi Deshpande, Chin Soon Wah |
| 2007 | Analyzing and addressing the impact of test fixture relays for multi-gigabit ATE I/O characterization applications. | Jose Moreira, Heidi Barnes, Guenter Hoersch |
| 2007 | High throughput non-contact SiP testing. | Brian Moore, Chris Sellathamby, Philippe Cauvet, Hrv Fleury, M. Paulson, Md. Mahbub Reja, Lin Fu, Brenda Bai, Edwin Walter Reid, Igor M. Filanovsky, Steven Slupsky |
| 2007 | Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip. | Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh |
| 2007 | Dependable clock distribution for crosstalk aware design. | Yukiya Miura |
| 2007 | Circuit failure prediction to overcome scaled CMOS reliability challenges. | Subhasish Mitra, Mridul Agarwal |
| 2007 | Novel compensation scheme for local clocks of high performance microprocessors. | Cecilia Metra, Martin Omaa, T. M. Mak, Simon Tam |
| 2007 | Enhanced testing of clock faults. | Teresa L. McLaurin, Rich Slobodnik, Kun-Han Tsai, Ana Keim |
| 2007 | Principles and results of some test cost reduction methods for ASICs. | Peter C. Maxwell |
| 2007 | A universal DC to logic performance correlation. | Andrew Marshall |
| 2007 | Testing of Vega2, a chip multi-processor with spare processors. | Samy Makar, Tony Altinis, Niteen Patkar, Janet Wu |
| 2007 | Modeling facet roughening errors in self-assembly by snake tile sets. | Xiaojun Ma, Jing Huang, Fabrizio Lombardi |
| 2007 | An efficient SAT-based path delay fault ATPG with an unified sensitization model. | Shun-Yen Lu, Ming-Ting Hsieh, Jing-Jia Liou |
| 2007 | Interconnect open defect diagnosis with minimal physical information. | Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang |
| 2007 | Efficient simulation of parametric faults for multi-stage analog circuits. | Fang Liu, Sule Ozev |
| 2007 | Test yield estimation for analog/RF circuits over multiple correlated measurements. | Fang Liu, Erkan Acar, Sule Ozev |