| 2007 | Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects. | Jeroen Geuzebroek, Erik Jan Marinissen, Ananta K. Majhi, Andreas Glowatz, Friedrich Hapke |
| 2007 | How to ensure zero defects from the beginning with semiconductor test methods. | Bernd Gessner |
| 2007 | On ATPG for multiple aggressor crosstalk faults in presence of gate delays. | Kunal P. Ganeshpure, Sandip Kundu |
| 2007 | Design for test features of the ARM clock control macro. | Frank Frederick, Teresa L. McLaurin |
| 2007 | On-chip timing uncertainty measurements on IBM microprocessors. | Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem |
| 2007 | Implementing bead probe technology for in-circuit test: A case study. | Mike Farrell, Glen Leinbach |
| 2007 | A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata. | Yongquan Fan, Yi Cai, Zeljko Zilic |
| 2007 | The new ATE: Protocol aware. | Andrew C. Evans |
| 2007 | IEEE P1581 can solve your board level memory cluster test problems. | Heiko Ehrenberg |
| 2007 | Which defects are most critical? optimizing test sets to minimize failures due to test escapes. | Jennifer Dworak |
| 2007 | PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. | V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti |
| 2007 | A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. | V. R. Devanathan, C. P. Ravikumar, V. Kamakoti |
| 2007 | IJTAG: The path to organized instrument connectivity. | Alfred L. Crouch |
| 2007 | Redefining and testing interconnect faults in Mesh NoCs. | rika F. Cota, Fernanda Lima Kastensmidt, Maico Cassel, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski |
| 2007 | Where is car IC testing going? | Steve Comen |
| 2007 | California scan architecture for high quality and low power testing. | Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey |
| 2007 | A matched expansion MEMS probe card with low CTE LTCC substrate. | Seong-Hun Choe, Shuji Tanaka, Masayoshi Esashi |
| 2007 | A practical approach to comprehensive system test & debug using boundary scan based test architecture. | Tapan J. Chakraborty, Chen-Huan Chiang, Bradford G. Van Treuren |
| 2007 | Protocol requirements in an SJTAG/IJTAG environment. | Gunnar Carlsson, Johan Holmqvist, Erik Larsson |
| 2007 | Management of common-mode currents in semiconductor ATE. | William J. Bowhers |
| 2007 | Delay fault simulation with bounded gate delay mode. | Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal |
| 2007 | Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. | Soumitra Bose, Vishwani D. Agrawal |
| 2007 | SiP-test: Predicting delivery quality. | Alex S. Biewenga, Frans G. M. de Jong |
| 2007 | Power dissipation, variations and nanoscale CMOS design: Test challenges and self-calibration/self-repair solutions. | Swarup Bhunia, Kaushik Roy |
| 2007 | Achieving serendipitous N-detect mark-offs in Multi-Capture-Clock scan patterns. | Gaurav Bhargava, Dale Meehl, James Sage |