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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2007Analyzing the risk of timing modeling based on path delay tests.Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir
2007An algorithm to evaluate wide-band quadrature mixers.Koji Asami
2007Automotive IC's: less testing, more prevention.Davide Appello
2007A comparative study of continuous sampling plans for functional board testing.Jukka Antila, Timo Karhu
2007On using lossless compression of debug data in embedded logic analysis.Ehab Anis, Nicola Nicolici
2007Cost effective manufacturing test using mission mode tests.Parmod Aggarwal
2007Low cost characterization of RF transceivers through IQ data analysis.Erkan Acar, Sule Ozev
2007Separating temperature effects from ring-oscillator readings to measure true IR-drop on a chip.Zahi S. Abuhamdeh, Vincent D'Alassandro, Richard Pico, Dale Montrone, Alfred L. Crouch, Andrew Tracy
2006BIST Power Reduction Using Scan-Chain Disable in the Cell Processor.Christian G. Zoellin, Hans-Joachim Wunderlich, Nicolas Mding, Jens Leenstra
2006Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits.Chong Zhao, Sujit Dey
2006ISI Injection Filter Designs Using PIN and Varactor Diodes for SerDes Testing on ATE.Fengming Zhang, Warren Necoechea
2006Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains.Hyunbean Yi, Jaehoon Song, Sungju Park
2006Self-Checking and Self-Diagnosing 32-bit Microprocessor Multiplier.Mahmut Yilmaz, Derek Hower, Sule Ozev, Daniel J. Sorin
2006Multi Strobe Circuit for 2.133GHz Memory Test System.Kazuhiro Yamamoto, Masakatsu Suda, Toshiyuki Okayasu, Hirokatsu Niijima, Koichi Tanaka
2006A Study of Per-Pin Timing Jitter Scope.Takahiro J. Yamaguchi, Satoshi Iwamoto, Masahiro Ishida, Mani Soma
2006Perfect data reconstruction algorithm of time interleaved ADCs.Fang Xu
2006A High Speed Reduced Pin Count JTAG Interface.Lee Whetsel
2006Power Supply Noise in Delay Testing.Jing Wang, D. M. H. Walker, Ananta K. Majhi, Bram Kruseman, Guido Gronthoud, Luis Elvira Villagra, Paul van de Wiel, Stefan Eichenberger
2006Design for Board and System Level Structural Test and Diagnosis.Toai Vo, Zhiyuan Wang, Ted Eaton, Pradipta Ghosh, Huai Li, Young Lee, Weili Wang, Hong Shin Jun, Rong Fang, Dan Singletary, Xinli Gu
2006Test Software Generation Productivity and Code Quality Improvement by applying Software Engineering Techniques.Stefan Vock, Markus Schmid, Hans Martin von Staudt
2006Novel Architecture for On-Chip AC Characterization of I/Os.N. Vijayaraghavan, Balwant Singh, Saurabh Singh, Vishal Srivastava
2006A Reconfigurable Built-In Self-Repair Scheme for Multiple Repairable RAMs in SOCs.Tsu-Wei Tseng, Jin-Fu Li, Chih-Chiang Hsu, Alex Pao, Kevin Chiu, Eliot Chen
2006Test Economics - What can a Board/System Test Engineer do to Influence Supply Operation Metrics.Sylvain Tourangeau, Bill Eklow
2006On-chip Test and Repair of Memories for Static and Dynamic Faults.Sanjay K. Thakur, Rubin A. Parekhji, Arun N. Chandorkar
2006Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O Interconnects.Hiren D. Thacker, James D. Meindl
1,4261,450 of 4,920← PreviousNext →

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