| 2006 | Improving Transition Fault Test Pattern Quality through At-Speed Diagnosis. | Nandu Tendolkar, Dawit Belete, Bill Schwarz, Bob Podnar, Akshay Gupta, Steve Karako, Wu-Tung Cheng, Alex Babin, Kun-Han Tsai, Nagesh Tamarapalli, Greg Aldrich |
| 2006 | Testing of UltraSPARC T1 Microprocessor and its Challenges. | P. J. Tan, Tung Le, Keng-Hian Ng, Prasad Mantri, James Westfall |
| 2006 | Test Compression for FPGAs. | Mehdi Baradaran Tahoori, Subhasish Mitra |
| 2006 | A Study of Implication Based Pseudo Functional Testing. | Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty |
| 2006 | Testing MRAM for Write Disturbance Fault. | Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao |
| 2006 | Analog Boundary-Scan Description Language (ABSDL) for Mixed-Signal Board Test. | Bambang Suparjo, Adam W. Ley, Adam Cron, Heiko Ehrenberg |
| 2006 | Structural Tests for Jitter Tolerance in SerDes Receivers. | Stephen K. Sunter, Aubin Roy |
| 2006 | High-Voltage and High-Power PLL Diagnostics using Advanced Cooling and Emission Images. | Franco Stellari, Peilin Song, Tim Diemoz, Alan J. Weger, Tami Vogel, Steven C. Wilson, John Pennings, Richard F. Rizzolo |
| 2006 | Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method. | Hongjoong Shin, Joonsung Park, Jacob A. Abraham |
| 2006 | Estimating Error Rate during Self-Test via One's Counting. | Shideh Shahidi, Sandeep K. Gupta |
| 2006 | Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling. | Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng |
| 2006 | Very-Low Voltage (VLV) and VLV Ratio (VLVR) Testing for Quality, Reliability, and Outlier Detection. | Jeffrey L. Roehr |
| 2006 | Fully-Digital Time-To-Digital Converter for ATE with Autonomous Calibration. | Jochen Rivoir |
| 2006 | Debug of the CELL Processor: Moving the Lab into Silicon. | Mack W. Riley, Nathan Chelstrom, Mike Genden, Shoji Sawamura |
| 2006 | Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. | Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski |
| 2006 | On-line Boundary-Scan Testing in Service of Extended Products. | Ilka Reis, Peter Collins, Marc van Houcke |
| 2006 | Lead Free Through Hole Technology (THT) and Contact Repeatability in In-Circuit Test. | Rosa D. Reinosa |
| 2006 | A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing. | Jeff Rearick, Aaron Volz |
| 2006 | A Survey of Test Problems and Solutions. | Jeff Rearick |
| 2006 | X-Press Compactor for 1000x Reduction of Test Data. | Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab |
| 2006 | What is DFM & DFY and Why Should I Care ? | Rajesh Raina |
| 2006 | Comparison of Delay Tests on Silicon. | Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore |
| 2006 | IEEE P1687: Toward Standardized Access of Embedded Instrumentation. | Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, Jean-Francois Cote |
| 2006 | Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. | Irith Pomeranz, Sudhakar M. Reddy |
| 2006 | Test Structure and Testing of the Microsoft XBOX 360 | Tung Pham, Brian Koehler, Daniel Young, Louis Bushard |