| 2006 | A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. | Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware |
| 2006 | Jump Simulation: A Technique for Fast and Precise Scan Chain Fault Diagnosis. | Yu-Long Kao, Wei-Shun Chuang, James Chien-Mo Li |
| 2006 | DIBPro: Automatic Diagnostic Program Generation Tool. | Venkat Kalyanaraman, Bruce C. Kim, Pramodchandran N. Variyam, Sasikumar Cherubal |
| 2006 | A Framework of High-quality Transition Fault ATPG for Scan Circuits. | Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato |
| 2006 | SiP-TAP: JTAG for SiP. | Frans G. M. de Jong, Alex S. Biewenga |
| 2006 | Structural Testing of High-Speed Serial Buses: A Case Study Analysis. | Eric Johnson |
| 2006 | Testing of Precision DACs Using Low-Resolution ADCs with Dithering. | Le Jin, Hosam Haggag, Randall L. Geiger, Degang Chen |
| 2006 | Linearity Test of Analog-to-Digital Converters Using Kalman Filtering. | Le Jin, Degang Chen, Randall L. Geiger |
| 2006 | At-Speed Structural Test For High-Performance ASICs. | Vikram Iyengar, Toshihiko Yokota, Kazuhiro Yamada, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Mark Johnson, Dave Milton, Mark Taylor, Frank Woytowich |
| 2006 | A Real-Time Delta-Time-to-Voltage Converter for Clock Jitter Measurement. | Kiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma |
| 2006 | Diagnosis with Limited Failure Information. | Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen |
| 2006 | Pattern Pruner: Automatic Pattern Size Reduction Method that Uses Computational Intelligence-Based Testing. | Eric Liau Chee Hong, Manfred Menke, Thomas Janik, Doris Schmitt-Landsiedel |
| 2006 | Bit Error Rate Estimation for Improving Jitter Testing of High-Speed Serial Links. | Dongwoo Hong, Kwang-Ting Cheng |
| 2006 | The Power of Exhaustive Bridge Diagnosis using IDDQ Speed, Confidence, and Resolution. | Doug Heaberlin |
| 2006 | Recognition of Sensitized Longest Paths in Transition Delay Test. | Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Noduyama, Yasuo Sato |
| 2006 | Massively Parallel Validation of High-Speed Serial Interfaces using Compact Instrument Modules. | Mohamed Hafed, Daniel Watkins, Clarence Tam, Bardia Pishdad |
| 2006 | Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. | Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham |
| 2006 | Data Analysis Techniques for CMOS Technology Characterization and Product Impact Assessment. | Anne Gattiker, Manjul Bhushan, Mark B. Ketchen |
| 2006 | A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing. | Hiroshi Furukawa, Xiaoqing Wen, Laung-Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu |
| 2006 | Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk. | Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, rika F. Cota |
| 2006 | Classifying Bad Chips and Ordering Test Sets. | Franois-Fabien Ferhani, Edward J. McCluskey |
| 2006 | Cost Effective Outliers Screening with Moving Limits and Correlation Testing for Analogue ICs. | Liquan Fang, Mohammed Lemnawar, Yizi Xing |
| 2006 | An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA. | Yongquan Fan, Yi Cai, Liming Fang, Anant Verma, William Burchanowski, Zeljko Zilic, Sandeep Kumar |
| 2006 | A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise. | Erdem Serkan Erdogan, Sule Ozev |
| 2006 | Combining Internal Probing with Artificial Neural Networks for Optimal RFIC Testing. | Sofiane Ellouz, Patrice Gamand, Christophe Kelma, Bertrand Vandewiele, Bruno Allard |