| 2006 | IEEE P1581 - Getting More Board Test Out of Boundary Scan. | Heiko Ehrenberg |
| 2006 | Optimizing the Cost of Test at Intel Using per Device Data. | Robert Edmondson, Gregory Iovino, Richard Kacprowicz |
| 2006 | Using Limited Dependence Sequential Expansion for Decompressing Test Vectors. | Avijit Dutta, Nur A. Touba |
| 2006 | Technique to Detect RF Interface and Contact Issues During Production Testing. | Martin Dresler |
| 2006 | Implementation of Solder-bead Probing in High Volume Manufacturing. | Madhavan Doraiswamy, James J. Grealish |
| 2006 | A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior. | Rao Desineni, Osei Poku, Ronald D. Blanton |
| 2006 | Integrated RF-CMOS Transceivers challenge RF Test. | Frank Demmerle |
| 2006 | Behavioral Test Economics. | Scott Davidson, Anthony P. Ambler, Helen Davidson |
| 2006 | OCI: Open Compression Interface. | Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie |
| 2006 | An Enhanced EDAC Methodology for Low Power PSRAM. | Po-Yuan Chen, Yi-Ting Yeh, Chao-Hsun Chen, Jen-Chieh Yeh, Cheng-Wen Wu, Jeng-Shen Lee, Yu-Chang Lin |
| 2006 | Characteristic States and Cooperative Game Based Search for Efficient Sequential ATPG and Design Validation. | Xiaoding Chen, Michael S. Hsiao |
| 2006 | Signature Based Diagnosis for Logic BIST. | Wu-Tung Cheng, Manish Sharma, Thomas Rinderknecht, Liyang Lai, Chris Hill |
| 2006 | Fault Coverage Estimation for Non-Random Functional Input Sequences. | Soumitra Bose, Vishwani D. Agrawal |
| 2006 | Diagnostic Test Generation for Arbitrary Faults. | Naresh K. Bhatti, Ronald D. Blanton |
| 2006 | Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues. | Ismet Bayraktaroglu, Jim Hunt, Daniel Watkins |
| 2006 | Defect-Oriented and Time-Constrained Wafer-Level Test-Length Selection for Core-Based Digital SoCs. | Sudarshan Bahukudumbi, Krishnendu Chakrabarty |
| 2006 | Test Data Compression of 100x for Scan-Based BIST. | Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Tatsuru Matsuo, Takahisa Hiraide, Hideaki Konishi, Michiaki Emori, Takashi Aikyo |
| 2006 | Embedded Memory Diagnosis: An Industrial Workflow. | Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda |
| 2006 | A Predictable Robust Fully Programmable Analog Gaussian Noise Source for Mixed-Signal/Digital ATE. | Sadok Aouini, Gordon W. Roberts |
| 2006 | Improving Precision Using Mixed-level Fault Diagnosis. | M. Enamul Amyeen, Debashis Nayak, Srikanth Venkataraman |
| 2006 | Seamless Integration of SER in Rewiring-Based Design Space Exploration. | Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris |
| 2006 | The Economics of Implementing Scan Compression to Reduce Test Data Volume and Test Application Time. | Chris Allsup |
| 2006 | DRAM-Specific Space of Memory Tests. | Zaid Al-Ars, Said Hamdioui, Ad J. van de Goor, Georgi Gaydadjiev, Jrg E. Vollrath |
| 2006 | Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation. | Selim Sermet Akbay, Jose L. Torres, Julie M. Rumer, Abhijit Chatterjee, Joel Amtsfield |
| 2006 | The Design and Validation of IP for DFM/DFY Assurance. | Robert C. Aitken |