| 2006 | Characterize Predicted vs Actual IR Drop in a Chip Using Scan Clocks. | Zahi S. Abuhamdeh, Philip Pears, Jeff Remmers, Alfred L. Crouch, Bob Hannagan |
| 2005 | IEEE 1500 utilization in SOC design and test. | Yervant Zorian, Avetik Yessayan |
| 2005 | Today's SOC test challenges. | Yervant Zorian |
| 2005 | Power-scan chain: design for analog testability. | Amir Zjajo, Henk Jan Bergveld, Rodger Schuttert, Jos Pineda de Gyvez |
| 2005 | A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits. | Chong Zhao, Xiaoliang Bai, Sujit Dey |
| 2005 | Low cost multisite testing of quadruple band GSM transceivers. | Larry Zhang, Dale Heaton, Hank Largey |
| 2005 | Jitter transformations in measurement instruments and discrepancies between measurement results. | Iliya Zamek, Steve Zamek |
| 2005 | Definitions of jitter measurement terms and relationships. | Iliya Zamek, Steve Zamek |
| 2005 | External memory BIST for system-in-package. | Kaname Yamasaki, Iwao Suzuki, Azumi Kobayashi, Keiichi Horie, Yasuharu Kobayashi, Hideyuki Aoki, Hideki Hayashi, Kenichi Tada, Koki Tsutsumida, Keiichi Higeta |
| 2005 | A wideband low-noise ATE-based method for measuring jitter in GHz signals. | Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma |
| 2005 | On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. | Qiang Xu, Nicola Nicolici |
| 2005 | I | Bin Xue, D. M. H. Walker |
| 2005 | Test compression and logic BIST at your fingertips. | Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu |
| 2005 | Position statement: "have we overcome the challenges associated with SoC and multi-core testing?". | Tim Wood |
| 2005 | Efficient compression of deterministic patterns into multiple PRPG seeds. | Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur |
| 2005 | Outsourcing DFT: it can be done but it isn't easy. | LeRoy Winemberg |
| 2005 | Low-capture-power test generation for scan-based at-speed testing. | Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
| 2005 | Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology. | Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Wei-Ting Liu, Ji-Jan Chen |
| 2005 | A vector-based approach for power supply noise analysis in test compaction. | Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker |
| 2005 | Test data compression for IP embedded cores using selective encoding of scan slices. | Zhanglei Wang, Krishnendu Chakrabarty |
| 2005 | Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics. | Zhanglei Wang, Krishnendu Chakrabarty |
| 2005 | XWRC: externally-loaded weighted random pattern testing for input test data compression. | Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar |
| 2005 | UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. | Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang |
| 2005 | Partnering with customer to achieve high yield. | James Wang |
| 2005 | Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain. | Tom Waayers, Richard Morren, Roberto Grandi |