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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2005A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set.Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis, Constantin Halatsis
2005Soft errors: is the concern for soft-errors overblown?Narayanan Vijaykrishnan
2005Achieving higher yield through diagnosis?Srikanth Venkataraman
2005Drive only at speed functional testing; one of the techniques Intel is using to control test costs.Mike Tripp, Silvio Picano, Baruch Schnarch
2005JTAG-based vector and chain management for system test.Bradford G. Van Treuren, Bryan E. Peterson, Jos M. Miranda
2005Logic proximity bridges.Eric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty
2005Methods for improving test compression.Nur A. Touba
2005An optimal test pattern selection method to improve the defect coverage.Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer
2005Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture.Nandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan
2005Business constraints drive test decisions - not vice versa.Sanjiv Taneja
2005Achieving higher yield through diagnosis.Nagesh Tamarapalli
2005Jitter spectrum analysis using continuous time interval analyzer (CTIA).Sassan Tabatabaei, Freddy Ben-Zeev, Touraj Farahmand
2005Diagnosis and analysis of an analog circuit failure using time resolved emission microscopy.Ahmed Syed, Richard F. Herlein, Ben Cain, Frank Sauk
2005Reducing test cost through the use of digital testers for analog tests.John Sweeney, Alan Tsefrekas
2005Structural tests for jitter tolerance in SerDes receivers.Stephen K. Sunter, Aubin Roy
2005Correct by construction is guaranteed to fail.Stephen K. Sunter
2005Defect-oriented testing and diagnosis of digital microfluidics-based biochips.Fei Su, William L. Hwang, Arindam Mukherjee, Krishnendu Chakrabarty
2005CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system.Masakatsu Suda, Kazuhiro Yamamoto, Toshiyuki Okayasu, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe
2005Enabling yield analysis with X-compact.Zoran Stanojevic, Ruifeng Guo, Subhasish Mitra, Srikanth Venkataraman
2005An advanced optical diagnostic technique of IBM z990 eServer microprocessor.Peilin Song, Franco Stellari, Bill Huott, Otto Wagner, Uma Srinivasan, Yuen H. Chan, Rick Rizzolo, H. J. Nam, James P. Eckhardt, Timothy G. McNamara, Ching-Lung Tong, Alan J. Weger, Moyra K. McManus
2005Guaranteed by design or guaranteed to fail or guaranteed by test? or ... neither?Mani Soma
2005How are we going to test SOC's on a board?Michael J. Smith
2005Reducing high-speed/RF test cost - guaranteed by design or guaranteed to fail?Mustapha Slamani
2005A self-timed structural test methodology for timing anomalies due to defects and process variations.Adit D. Singh
2005Functional vs. multi-VDD testing of RF circuits.Estella Silva, Jos Pineda de Gyvez, Guido Gronthoud
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