| 2005 | Test generation for ultra-high-speed asynchronous pipelines. | Feng Shi, Yiorgos Makris, Steven M. Nowick, Montek Singh |
| 2005 | X-filter: filtering unknowns from compacted test responses. | Manish Sharma, Wu-Tung Cheng |
| 2005 | A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. | Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy |
| 2005 | Noncontact wafer probe using wireless probe cards. | Chris Sellathamby, Md. Mahbub Reja, Lin Fu, Brenda Bai, Edwin Walter Reid, Steven Slupsky, Igor M. Filanovsky, Kris Iniewski |
| 2005 | Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis. | Chris Schuermyer, Kevin Cota, Robert Madge, Brady Benware |
| 2005 | Achieving higher yield through diagnosis-the ASIC perspective. | Chris Schuermyer |
| 2005 | A novel process and hardware architecture to reduce burn-in cost. | Chris Schroeder, Jin Pan, Todd Albertson |
| 2005 | Panel: business constraints drive test decisions. | Jeff Schneider |
| 2005 | Invisible delay quality - SDQM model lights up what could not be seen. | Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara |
| 2005 | The concern for soft errors is not overblown. | Pia N. Sanda |
| 2005 | Efficient SAT-based combinational ATPG using multi-level don't-cares. | Nikhil Saluja, Sunil P. Khatri |
| 2005 | Verifying flying prober performance - fitness is survival. | Bob Russell |
| 2005 | The case for outsourcing DFT. | Jeffrey L. Roehr |
| 2005 | Board and system test with SoC DFT. | Gordon D. Robinson |
| 2005 | Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. | Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski |
| 2005 | Testability features of the first-generation CELL processor. | Mack W. Riley, Louis B. Bushard, Nathan Paul Chelstrom, Naoki Kiryu, Steven Ross Ferguson |
| 2005 | Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case study. | Jeff Remmers, Darin Lee, Richard Fisette |
| 2005 | Effect of lead free solders on in-circuit test process. | Rosa D. Reinosa |
| 2005 | Calibrating clock stretch during AC scan testing. | Jeff Rearick, Richard Rodgers |
| 2005 | IJTAG (internal JTAG): a step toward a DFT standard. | Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts |
| 2005 | Test compression - real issues and matching solutions. | Janusz Rajski |
| 2005 | Have we overcome the challenges associated with SoC and multi-core testing? | Rajesh Raina |
| 2005 | Have we overcome the challenges associated with SoC and multi-core testing? | Rajesh Raina |
| 2005 | Is the concern for soft-error overblown? | Rajesh Raina |
| 2005 | Is the concern for soft-error overblown? | Rajesh Raina |