| 2002 | Scan Power Reduction Through Test Data Transition Frequency Analysis. | Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu |
| 2002 | Test and Repair of Non-Volatile Commodity and Embedded Memories (NAND Flash Memory). | Riichiro Shirota |
| 2002 | New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing. | Masashi Shimanouchi |
| 2002 | Finding a Small Set of Longest Testable Paths that Cover Every Gate. | Manish Sharma, Janak H. Patel |
| 2002 | Parametric Failures in CMOS ICs - A Defect-Based Analysis. | Jaume Segura, Ali Keshavarzi, Jerry M. Soden, Charles F. Hawkins |
| 2002 | Mission Possible? Open Architecture ATE. | Paul F. Scrivens |
| 2002 | Multi-Gigahertz Digital Test Challenges and Techniques. | Ulrich Schoettmer |
| 2002 | Scan-Based Transition Fault Testing - Implementation and Low Cost Test Challenges . | Jayashree Saxena, Kenneth M. Butler, John Gatt, R. Raghuraman, Sudheendra Phani Kumar, Supatra Basu, David J. Campbell, John Berech |
| 2002 | A Persistent Diagnostic Technique for Unstable Defects. | Yasuo Sato, Iwao Yamazaki, Hiroki Yamanaka, Toshio Ikeda, Masahiro Takakura |
| 2002 | Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. | Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal |
| 2002 | Physical Principles of Interface Design. | Todd Sargent |
| 2002 | RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST. | Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira, Salvador Manich, Rosa Rodrguez-Montas, Joan Figueras |
| 2002 | Multi-Gigahertz Digital Test Challenges and Techniques. | Manoj Sachdev |
| 2002 | High Accuracy Stimulus Generation for A/D Converter BIST. | Aubin Roy, Stephen K. Sunter, Alessandra Fudoli, Davide Appello |
| 2002 | Is an Open Architecture Tester Really Achievable? | Paul D. Roddy |
| 2002 | Board Test: Wanted Dead or Alive. | Gordon D. Robinson |
| 2002 | Mixed-Signal BIST: Fact or Fiction. | Gordon W. Roberts |
| 2002 | On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. | Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita |
| 2002 | Can IC Test Learn from How a Tester is Tested. | Rochit Rajsuman |
| 2002 | Testing The Tester. | Rochit Rajsuman |
| 2002 | Testing The Tester. | Rochit Rajsuman |
| 2002 | Embedded Deterministic Test for Low-Cost Manufacturing Test. | Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian |
| 2002 | Wafer-Level Defect-Based Testing Using Enhanced Voltage Stress and Statistical Test Data Evaluation. | Minh Quach, Tuan Pham, Tim Figal, Bob Kopitzke, Pete O'Neill |
| 2002 | Silicon Symptoms to Solutions: Applying Design for Debug Techniques. | Carol Pyron, Rekha Bangalore, Dawit Belete, Jason Goertz, Ashutosh Razdan, Denise Younger |
| 2002 | Scan and BIST Can Almost Achieve Test Quality Levels. | Carol Pyron |