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IEEE International Test Conference

ITC

A

CORE rank

CORE rank (raw)

A

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Papers per year

1981207 peak2025

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

YearTitleAuthors
2001A building block BIST methodology for SOC designs: a case study.Patrick R. Gallagher Jr., Vivek Chickermane, Steven Gregor, Thomas S. Pierre
2001AMLETO: a multi-language environment for functional test generation.Alessandro Fin, Franco Fummi, Graziano Pravadelli
2001Moving from mixed signal to RF test hardware development.John Ferrario, Randy Wolf, Hanyi Ding
2001Unsafe board states during PC-based boundary-scan testing.William Eklow, Richard M. Sedmak, Dan Singletary, Toai Vo
2001Tailoring ATPG for embedded testing.Rainer Dorsch, Hans-Joachim Wunderlich
2001BIST and fault insertion re-use in telecom systems.Snezana Dikic, Lars-Johan Fritz, Dario Dell'Aquia
2001Practical, non-invasive optical probing for flip-chip devices.G. Dajee, Norman Goldblatt, Ted R. Lundquist, Steven Kasapi, Keneth R. Wilsher
2001Neighbor selection for variance reduction in I_DDQ and other parametric data.W. Robert Daasch, Kevin Cota, James McNames, Robert Madge
2001Scan test sequencing hardware for structural test.Jamie Cullen
2001AC-JTAG: empowering JTAG beyond testing DC nets.Sung Soo Chung, Sanghyeon Baeg
2001GRAAL: a tool for highly dependable SRAMs generation.Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Franco Bigongiari
2001A high-resolution jitter measurement technique using ADC sampling.Sasikumar Cherubal, Abhijit Chatterjee
2001Crosstalk test generation on pseudo industrial circuits: a case study.Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer
2001Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring.John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
2001When zero picoseconds edge placement accuracy is not enough.John Cheng
2001A synthesizable, fast and high-resolution timing measurement device using a component-invariant vernier delay line.Antonio H. Chan, Gordon W. Roberts
2001Use of BIST in Sun FireJohn Braden, Qing Lin, Brian Smith
2001Optimal production test times through adaptive test programming.Scott Benner, Oluseyi Boroffice
2001Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm.Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski
2001OPMISR: the foundation for compressed ATPG vectors.Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Knemann, Andrej Ferko
2001Estimating burn-in fall-out for redundant memory.Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
2001Towards a unified test process: from UML to end-of-line functional test.Andrea Baldini, Alfredo Benso, Paolo Prinetto, Sergio Mo, Andrea Taddei
2001Testing interconnects for noise and skew in gigahertz SoCs.Amir Attarha, Mehrdad Nourani
2001A practical guide to combining ICT & boundary scan testing.Alan Albee
2001Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs.Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter
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