IEEE International Test Conference

ITC

CORE rank

CORE rank (raw)

Fields of research

Computer Systems Engineering

Papers indexed

4,920

1981–2025

Best Computer Systems Engineering conferences

Papers per year

1981207 peak2025

Most published authors

ITC papers

4,920 records sourced from DBLP. Search titles, filter by year, sort by recency.

Year	Title	Authors
2001	Combinational test generation for various classes of acyclic sequential circuits.	Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja
2001	A new methodology for improved tester utilization.	Ajay Khoche, Rohit Kapur, David Armstrong, Thomas W. Williams, Mick Tegethoff, Jochen Rivoir
2001	Extreme-voltage stress vector generation of analog CMOS ICs for gate-oxide reliability enhancement.	Mohammad Athar Khalil, Chin-Long Wey
2001	Using a hierarchical DfT methodology in high frequency processor designs for improved delay fault testability.	Michael Kessler, Gundolf Kiefer, Jens Leenstra, Knut Schnemann, Thomas Schwarz, Hans-Joachim Wunderlich
2001	On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits.	Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu
2001	Terabit-per-second automated digital testing.	David C. Keezer, Q. Zhou, C. Bair, J. Kuan, B. Poole
2001	Tester retargetable patterns.	Rohit Kapur, Thomas W. Williams
2001	CTL the language for describing core-based test.	Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay
2001	Test methodology for the McKinley processor.	Don Douglas Josephson, Steve Poehlman, Vincent Govan, Clint Mumford
2001	Debug methodology for the McKinley processor.	Don Douglas Josephson, Steve Poehhnan, Vincent Govan
2001	Testing and programming flash memories on assemblies during high volume production.	Frans G. M. de Jong, Alex S. Biewenga, D. C. L. (Erik) van Geest, T. F. Waayers
2001	Embedded DRAM built in self test and methodology for test insertion.	Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek
2001	Testing beyond EPA: TDF methodology solutions matrix.	Sunil K. Jain, Greg P. Chema
2001	Test wrapper and test access mechanism co-optimization for system-on-chip.	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen
2001	On RTL scan design.	Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy
2001	A token scan architecture for low power testing.	Tsung-Chu Huang, Kuen-Jong Lee
2001	A case study on the implementation of the Illinois Scan Architecture.	Frank F. Hsu, Kenneth M. Butler, Janak H. Patel
2001	A built-in timing parametric measurement unit.	Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
2001	Test path simulation and characterisation.	Klaus Helmreich
2001	Hierarchical boundary-scan: a Scan Chip-Set solution.	Stephen Harrison, Peter Collins, Greg Noeninckx, Peter Horwood
2001	BIST-based delay path testing in FPGA architectures.	Ian G. Harris, Premachandran R. Menon, Russell Tessier
2001	A stand-alone integrated test core for time and frequency domain measurements.	Mohamed M. Hafed, Nazmy Abaskharoun, Gordon W. Roberts
2001	A technique for fault diagnosis of defects in scan chains.	Ruifeng Guo, Srikanth Venkataraman
2001	An effort-minimized logic BIST implementation method.	Xinli Gu, Sung Soo Chung, Frank Tsang, Jan Arild Tofte, Hamid Rahmanian
2001	Implicit functionality and multiple branch coverage (IFMB): a testability metric for RT-level.	Fernando M. Gonalves, Marcelino B. Santos, Isabel C. Teixeira, Joo Paulo Teixeira

2,401–2,425 of 4,920← Previous Next →

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