| 2000 | Wrapper design for embedded core test. | Yervant Zorian, Erik Jan Marinissen, Maurice Lousberg, Sandeep Kumar Goel |
| 2000 | On using IEEE P1500 SECT for test plug-n-play. | Yervant Zorian, Erik Jan Marinissen, Rohit Kapur |
| 2000 | Analysis of interconnect crosstalk defect coverage of test sets. | Yi Zhao, Sujit Dey |
| 2000 | A domain coverage metric for the validation of behavioral VHDL descriptions. | Qiushuang Zhang, Ian G. Harris |
| 2000 | Self test architecture for testing complex memory structures. | Kamran Zarrineh, R. Dean Adams, Thomas J. Eckenrode, Steven P. Gregor |
| 2000 | A scalable and efficient methodology to extract two node bridges from large industrial circuits. | Sujit T. Zachariah, Sreejit Chakravarty |
| 2000 | Diagnostic test generation for sequential circuits. | Xiaoming Yu, Jue Wu, Elizabeth M. Rudnick |
| 2000 | Si-emulation: system verification using simulation and emulation. | Zan Yang, Byeong Min, Gwan Choi |
| 2000 | Jitter measurements of a PowerPC | Takahiro J. Yamaguchi, Mani Soma, David Halter, Jim Nissen, Rajesh Raina, Masahiro Ishida, Toshifumi Watanabe |
| 2000 | Non-scan design for testability for synchronous sequential circuits based on conflict analysis. | Dong Xiang, Yi Xu, Hideo Fujiwara |
| 2000 | Optimizing the flattened test-generation model for very large designs. | Peter Wohl, John A. Waicukauski |
| 2000 | Adapting scan architectures for low power operation. | Lee Whetsel |
| 2000 | Exploiting don't cares to enhance functional tests. | Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr |
| 2000 | POIROT: a logic fault diagnosis tool and its applications. | Srikanth Venkataraman, Scott Brady Drummonds |
| 2000 | Measuring code edges of ADCs using interpolation and its application to offset and gain error testing. | Pramodchandran N. Variyam, Vinay Agrawal |
| 2000 | Increasing the IDDQ test resolution using current prediction. | Pramodchandran N. Variyam |
| 2000 | Improving Delta-I_DDQ-based test methods. | Claude Thibeault |
| 2000 | Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
| 2000 | Novel technique for built-in self-test of FPGA interconnects. | Xiaoling Sun, Jian Xu, Ben Chan, Pieter M. Trouborst |
| 2000 | Bridging fault extraction from physical design data for manufacturing test development. | Charles E. Stroud, John Marty Emmert, John R. Bailey, Khushru S. Chhor, Dragan Nikolic |
| 2000 | Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. | Zoran Stanojevic, Hari Balachandran, D. M. H. Walker, Fred Lakbani, Jayashree Saxena, Kenneth M. Butler |
| 2000 | An improved fault diagnosis algorithm based on path tracing with dynamic circuit extraction. | Kazuki Shigeta, Toshio Ishiyama |
| 2000 | Enhanced delay defect coverage with path-segments. | Manish Sharma, Janak H. Patel |
| 2000 | Device interfacing: the weakest link in the chain to break into the giga bit domain? | Ulrich Schoettmer, Chris Wagner, Tom Bleakley |
| 2000 | It isn't just testing anymore (REDUX). | Stephen F. Scheiber |