| 1994 | Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. | Harry Hengster, Rolf Drechsler, Bernd Becker |
| 1994 | Application of High-Level Synthesis in an Industrial Project. | Ahmed Hemani, Brje Karlsson, Mats Fredriksson, Kurt Nordqvist, Bjrn Fjellborg |
| 1994 | Multiple Fault Testing in Analog Circuits. | Naim Ben-Hamida, Bozena Kaminska |
| 1994 | High Speed Digital Filtering on SRAM-Based FPGAs. | Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal |
| 1994 | A 600MHz Half-Bit Level Pipelined Multiplier Macrocell. | Debabrata Ghosh, Shamik Sural, S. K. Nandy |
| 1994 | TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. | Debabrata Ghosh, S. K. Nandy, K. Parthasarathy |
| 1994 | Design of an Application Specific VLSI Chip for Image Rotation. | Indradeep Ghosh, Bandana Majumdar |
| 1994 | OTA Based Neural Network Architectures with On-Chip Tuning of Synapses. | Joydeep Ghosh, Patrick LaCour, Spence Jackson |
| 1994 | Response Pipelined CAM Chips: The First Generation and Beyond. | Kanad Ghose, V. Anand Dharmaraj |
| 1994 | HSIM1 and HSIM2: Object Oriented Algorithms for VHDL Simulation. | Neeta Ganguly, Vijay Pitchumani |
| 1994 | An Algorithm to Test Reconfigured RAMs. | Manoj Franklin, Kewal K. Saluja |
| 1994 | SAGA: A Unification of the Genetic Algorithm with Simulated Annealing and its Application to Macro-Cell Placement. | Henrik Esbensen, Pinaki Mazumder |
| 1994 | Analog Modeling Using Event-Driven HDL's. | Dundar Dumlugol, Don Webber, Rajeev Madhavan |
| 1994 | On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. | Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi |
| 1994 | Multiobjective Search in VLSI Design. | Pallab Dasgupta, Prasenjit Mitra, P. P. Chakrabarti, S. C. De Sarkar |
| 1994 | High Performance Over-the-Cell Routing. | Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani |
| 1994 | On the Brink of a New Era in VLSI Design. | Joseph B. Costello |
| 1994 | Architecture for VLSI Design of CA Based Byte Error Correcting Code Decoders. | Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri |
| 1994 | Cellular Automata Based VLSI Architecture for Computing Multiplication and Inverses in GF (2 | P. Pal Chowdhury, R. Barua |
| 1994 | Detailed Routing of Multi-Terminal Nets in FPGAs. | Amit Chowdhary, Dinesh Bhatia |
| 1994 | Power Constraint Scheduling of Tests. | Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal |
| 1994 | ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis. | Samit Chaudhuri, Robert A. Walker |
| 1994 | Synthesis of Low Power Linear DSP Circuits Using Activity Metrics. | Abhijit Chatterjee, Rabindra K. Roy |
| 1994 | Gigachip Technology and the Signal Processing Revolution. | Pallab K. Chatterjee |
| 1994 | Energy Efficient Programmable Computation. | Anantha P. Chandrakasan, Mani B. Srivastava, Robert W. Brodersen |