| 1994 | Untitled record | Sreejit Chakravarty, Sivaprakasam Suresh |
| 1994 | Synthesis of Initializable Asynchronous Circuits. | Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan |
| 1994 | Mechanical Identification of Inductive Properties During Verification of Finite State Machines. | I. Chakrabarti, Dipankar Sarkar |
| 1994 | A Linear Systolic Array for LU Decomposition. | Emmanuel Casseau, Dominique Degrugillier |
| 1994 | Testable Realizations of CMOS Combinatorial Circuits for Voltage and Current Testing. | K. Biswas, Suresh Rai |
| 1994 | Over-the-Cell Routing Algorithms for Industrial Cell Models. | Siddharth Bhingarde, Rafay Khawaja, Anand Panyam, Naveed A. Sherwani |
| 1994 | A VLSI Architecture of an Inverse Discrete Cosine Transform. | Arup K. Bhattacharya, Syed S. Haider |
| 1994 | Hierarchical Reconfiguration of VLSI/WSI Arrays. | Dinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori |
| 1994 | Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs. | Dharmavani Bhagavathi, Stephan Olariu, James L. Schwing, Jingyuan Zhang |
| 1994 | LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS Circuits. | A. Bandyopadhyay, P. R. Verma, A. B. Bhattacharyya, M. J. Zarabi |
| 1994 | GLOVE: A Graph-Based Layout Verifier. | Cyrus Bamji, Jonathan Allen |
| 1994 | An Efficient Hybrid Heuristic for the Gate Matrix Layout Problem in VLSI Design. | Tanuj Bagchi, Sajal K. Das |
| 1994 | On Testability of Differential Split-Level CMOS Circuits. | S. M. Aziz, W. A. J. Waller |
| 1994 | SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI Circuits. | Abhaya Asthana, Mike Laznovsky, Boyd Mathews |
| 1994 | A CORDIC Based Programmable DXT Processor Array. | V. K. Anuradha, V. Visvanathan |
| 1994 | Flipping Modules to Improve Circuit Performance and Routability. | Keumog Ahn, Sartaj Sahni |
| 1994 | Parallel Model Evaluation for Circuit Simulation on the PACE Multiprocessor. | Prathima Agrawal, Sanjay Goil, Sally Liu, John A. Trotter |
| 1994 | On the Synthesis of Gate Matrix Layout. | Reena Agarwal, Indranil Sengupta |
| 1993 | Synthesis of Hazard-free Asynchronous Circuits from Generalized Signal-Transition Graphs. | Alexandre Yakovlev |
| 1993 | An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis. | Thomas Charles Wilson, Nilanjan Mukherjee, Manoj K. Garg, Dilip K. Banerji |
| 1993 | Harmonic Scheduling: A Technique for Scheduling Beyond Loop-Carried Dependencies. | Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau |
| 1993 | High-Speed A/D-D/A Conversion System with Flexible Testing Capabilities. | Joo C. Vital, Jos E. Franca |
| 1993 | An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. | V. Visvanathan, Nibedita Mohanty, S. Ramanathan |
| 1993 | A Module Generator Development Environment: Area Estimation and Design-Space Exploration Encapsulation. | Akhilesh Tyagi |
| 1993 | Parallel Network Primal-Dual Method on a Shared Memory Multiprocessor and a Unified Approach to VLSI Layout Compaction and Wire Balancing. | Krishnaiyan Thulasiraman, Prasad R. Chalasani, Parimala Thulasiraman, M. A. Comeau |