| 1993 | A Simulation-Based Test Generation Scheme Using Genetic Algorithms. | M. Srinivas, Lalit M. Patnaik |
| 1993 | A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. | Dinesh Somasekhar, V. Visvanathan |
| 1993 | A Heuristic for Decomposition in Multi-Level Logic Optimization. | Vinaya Kumar Singh, Ajit Arvind Diwan |
| 1993 | Export of VLSI Design and CAD: Present and Future. | Sunil D. Sherlekar |
| 1993 | A Carry Select Adder with Conflict Free Bypass Circuit. | M. Shamanna, Sterling R. Whitaker |
| 1993 | Genetic Beam Search for Gate Matrix Layout. | Khushro Shahookar, W. Khamisani, Pinaki Mazumder, Sudhakar M. Reddy |
| 1993 | Hardware Algorithms for Polygon Matching. | Raghu Sastry, N. Ranganathan, Horst Bunke |
| 1993 | DESSERT: Design Space Exploration of RT Level Components. | M. V. Rao, M. Balakrishnan, Anshul Kumar |
| 1993 | A PLA-Based FSM Design Technique. | S. Raman, M. M. Hasan |
| 1993 | A Methodology for Generating Application Specific Tree Multipliers. | S. Ramanathan, Nibedita Mohanty, V. Visvanathan |
| 1993 | Coverage of Bridging Faults by Random Testing in I | Rochit Rajsuman, David A. Penry |
| 1993 | A Reconfigurable Arithmetic Processor. | Arjun Rajagopal, Belli Kuttanna, Balaji Janakiraman, Rajarshi Mukherjee, Joy Shetler |
| 1993 | A Partition Approach to Find the Length of the Longest Common Subsequence. | Chowdhury S. Rahman, Mi Lu |
| 1993 | Preparing Engineers to Meet the Challenges of the 21st Century Through VLSI Education. | Kanti Prasad, Aditya Goel |
| 1993 | On Unified Delay Fault Testing. | Ankan K. Pramanick, Sudhakar M. Reddy |
| 1993 | On the Generation of Weights for Weighted Pseudo Random Testing. | Irith Pomeranz, Sudhakar M. Reddy |
| 1993 | State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. | Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar |
| 1993 | Area Efficient VLSI Design with Cells of Controllable Complexity. | G. Pannerselvam, A. Sarkar, Subir Bandyopadhyay, Graham A. Jullien |
| 1993 | NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic. | Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta |
| 1993 | Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits. | Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni |
| 1993 | Algorithm-Based Concurrent Error Detection for FFT Networks. | Choong Gun Oh, Hee Yong Youn, Vijay K. Raj |
| 1993 | Delay Fault Test Generation with Cellular Automata. | Sukumar Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy |
| 1993 | Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. | Ravindranath Naiknaware, G. N. Nandakumar, Rajeev Arora, John Larkin |
| 1993 | CAE in Requirements Definition and Specification for Complex Microelectronic Systems. | Klaus D. Mller-Glaser, Jrgen Bortolazzi, Yankin Tanurhan, Johannes Ernst |
| 1993 | Combining State Assignment with PLA Folding. | Chunduri Rama Mohan, Partha Pratim Chakrabarti, Sujoy Ghose |