| 1993 | A Scheme for Synthesizing Testable VLSI Designs with Minimum Area Overhead. | Biswadip Mitra, Parimal Pal Chaudhuri |
| 1993 | A Novel Scheme for Synthesis of Easily Testable Finite State Machines Using Cellular Automata. | Susanta Misra, Biswadip Mitra, Parimal Pal Chaudhuri |
| 1993 | Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. | Mahesh Mehendale, Kaushik Roy |
| 1993 | Minimization of Logic Functions Using Essential Signature Sets. | Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
| 1993 | A Multilayered Feed Forward Neural Network Suitable for VLSI Implementation. | Himanshu S. Mazumdar |
| 1993 | BEST: Bond Editor and Test Vector Translator. | P. Marimuthu, K. S. Raghunathan |
| 1993 | Statistical Analysis of Controllability. | Amitava Majumdar, Sarma Sastry |
| 1993 | Euclidean Shortest Path Problem with Rectilinear Obstacles. | Joon Shik Lim, S. Sitharama Iyengar, Si-Qing Zheng |
| 1993 | A Shared Memory Parallel Algorithm for Logic Synthesis. | Chieng-Fai Lim, Prithviraj Banerjee, Kaushik De, Saburo Muroga |
| 1993 | Architecture of a Min-Max Simulator on MARS. | Kumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal |
| 1993 | Efficient Technique to Reduce Gate Evaluations and Speed Up Fault Simulation. | P. R. Suresh Kumar, Mandyam-Komar Srinivas, James Jacob |
| 1993 | PLATO: A Tool for Computation of Exact Signal Probabilities. | B. Krieger |
| 1993 | SIGMA: A VLSI Chip for Galois Field GF(2 | Mario Kovac, N. Ranganathan, M. Varanasi |
| 1993 | A Mechanism for Fine-Grain Concurrent Sharing of Design Data Among CAD Tools. | Peter M. Kist, N. Simon, Mattie N. Sim, E. Marks, Kees Schot, A. Sarotama |
| 1993 | Optimizations for Behavioral/RTL Simulation. | Sankaran Karthik, Jacob A. Abraham, Raymond P. Voith |
| 1993 | On the History and Future Detecion of VLSI Design and CAD - Japanese Perspective. | Osamu Karatsu |
| 1993 | CACOP - A Random Pattern Testability Analyzer. | Wen-Ben Jone, Sunil R. Das |
| 1993 | Untitled record | Byung Wook Jeon, Chidchanok Lursinsap |
| 1993 | Rate-Optimal DSP Synthesis by Pipeline and Minimum Undolding. | Lih-Gwo Jeng, Liang-Gee Chen |
| 1993 | GB: A New Grid-Based Binding Approach for High-Level Synthesis. | Hyuk-Jae Jang, Barry M. Pangrle |
| 1993 | A Multiple Terminal Net Routing Algorithm Using Failure Prediction. | Ed P. Huijbregts, Jochen A. G. Jess |
| 1993 | Self-Organization and its Application to Binding. | Ahmed Hemani |
| 1993 | Performance Aspects of Gate Matrix Layout. | Bjarne Hald, Jan Madsen |
| 1993 | A Practical Approach to Layout Optimization. | Rajeev Govindan, Michael A. Langston, Siddharthan Ramachandramurthi |
| 1993 | An Integrated Technology CAD System for Process and Device Designers. | K. S. V. Gopalarao, Uttiya Dasgupta, Rajeev Jain, Duane S. Boning, Purnendu K. Mozumder, V. Chandramouli |